Joon-Yeong Lee

TL;DR: A 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM) that accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller.

TL;DR: This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

TL;DR: In this paper, a new interconnect called electrical tube (E-TUBE) is proposed as a cost-and-power-effective all-electricaldomain wideband waveguide solution for high-speed, high-volume, and short-reach communication links.

TL;DR: The minimum bound of the mean-squared phase-error of a bang-bang (BB) clock-and-data recovery (CDR) circuit under the condition of random phase tracking is presented.

TL;DR: This paper describes a 10-Gb/s clock-and-data recovery with a background optimum loop-bandwidth calibrator that automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory.