Hyosup Won

TL;DR: A 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM) that accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller.

TL;DR: This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

TL;DR: The measurement results show that the proposed design offers a lower frequency offset and clock noise floor under channel dispersion, as compared with conventional designs.

TL;DR: An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) that finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance is proposed.

TL;DR: The proposed EDC overcomes the chirp-induced dispersion via a nonlinear equalizer at the receiver and a pattern-dependent pre-compensator at the transmitter.