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Wei Deng
Researcher at Tsinghua University
Publications - 111
Citations - 1509
Wei Deng is an academic researcher from Tsinghua University. The author has contributed to research in topics: Phase-locked loop & Phase noise. The author has an hindex of 19, co-authored 86 publications receiving 1135 citations. Previous affiliations of Wei Deng include Tokyo Institute of Technology & Apple Inc..
Papers
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Journal ArticleDOI
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
Wei Deng,Dongsheng Yang,Tomohiro Ueno,Teerachot Siriburanon,Satoshi Kondo,Kenichi Okada,Akira Matsuzawa +6 more
TL;DR: This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor.
Journal ArticleDOI
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing
TL;DR: A feedback class-C voltage-controlled oscillator that has robust start-up and a large oscillation amplitude and transforms automatically into an amplitude-enhanced class- C VCO when it reaches steady-state to give improved noise performance is proposed.
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A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration
Ahmed Eleojo Musa,Wei Deng,Teerachot Siriburanon,Masaya Miyahara,Kenichi Okada,Akira Matsuzawa +5 more
TL;DR: The IL-ADPLL is implemented in a 65 nm CMOS process and measurement results show that it achieves a 0.7ps RMS jitter at 1.2 GHz while having 1.6 mW and 0.97 mW power consumption with and without intermittent operation resulting in an FOM of -243 dB.
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A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad
Teerachot Siriburanon,Satoshi Kondo,Makihiko Katsuragi,Hanli Liu,Kento Kimura,Wei Deng,Kenichi Okada,Akira Matsuzawa +7 more
TL;DR: This paper presents a low-power low-noise 60 GHz frequency synthesizer using a 20 GHz subsampling phase-locked loop (SS-PLL) and a 60 GHz tail-coupling quadrature injection-locked oscillator (QILO) which results in a lower in-band phase noise and out-of- band phase noise, respectively.
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A Fractional- N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
Aravind Tharayil Narayanan,Makihiko Katsuragi,Kento Kimura,Satoshi Kondo,Korkut Kaan Tokgoz,Kengo Nakata,Wei Deng,Kenichi Okada,Akira Matsuzawa +8 more
TL;DR: A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation.