Simulation and the monte carlo method

A long-range UHF RF identification (RFID) sensor has been designed using a 0.35- ?m CMOS standard process. The power-optimized tag, combined with the ultralow-power temperature sensor, allows an ID and a temperature reading range of 2 m from a 2-W effective radiated power output power reader. The temperature sensor is based on a ring oscillator, where the temperature dependence of the oscillation frequency is used for thermal sensing. The temperature sensor exhibits a resolution of 0.035°C and an inaccuracy value lower than 0.1°C in the range from 35°C to 45°C after two-point calibration. The average power consumption of the temperature sensor is only 110 nW at ten conversions per second while keeping a high resolution and accuracy. These properties allow the use of the RFID as a batteryless sensor in a wireless human body temperature monitoring system.

Full Passive UHF Tag With a Temperature Sensor Suitable for Human Body Temperature Monitoring

Fast and reliable time and frequency synchronization is crucial for packet-based orthogonal frequency division multiplex (OFDM) systems. In this paper we compare and analyze preambles for OFDM systems based on repeated OFDM data symbols or repeated short pseudonoise sequences (PN-sequences). We make an analytical evaluation for AWGN channels and simulate the performance in oneand two-tap Rayleigh fading channels. The PN-based preamble gives better detection properties in terms of lower false detection probability and lower probability of missing the synchronization signal. The PN-based preamble has low peak-to-average power ratio and it makes it possible to use an ADC with one-bit quantization in stand-by mode. For frequency offset estimation both preambles give similar performance, but the PN-based preamble allows for a greater reduction in stand-by mode power consumption.

Time and Frequency Synchronization for BRAN using PN-sequence Preambles

The appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) FFT architectures. In feedforward architectures radix-2k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

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Pipelined Radix- $2^{k}$ Feedforward FFT Architectures

Linear signal transforms such as the discrete Fourier transform (DFT) are very widely used in digital signal processing and other domains. Due to high performance or efficiency requirements, these transforms are often implemented in hardware. This implementation is challenging due to the large number of algorithmic options (e.g., fast Fourier transform algorithms or FFTs), the variety of ways that a fixed algorithm can be mapped to a sequential datapath, and the design of the components of this datapath. The best choices depend heavily on the resource budget and the performance goals of the target application. Thus, it is difficult for a designer to determine which set of options will best meet a given set of requirements.In this article we introduce the Spiral hardware generation framework and system for linear transforms. The system takes a problem specification as input as well as directives that define characteristics of the desired datapath. Using a mathematical language to represent and explore transform algorithms and datapath characteristics, the system automatically generates an algorithm, maps it to a datapath, and outputs a synthesizable register transfer level Verilog description suitable for FPGA or ASIC implementation. The quality of the generated designs rivals the best available handwritten IP cores.

/pdf/computer-generation-of-hardware-for-linear-digital-signal-475b6r4dak.pdf

Computer Generation of Hardware for Linear Digital Signal Processing Transforms

This paper proposes to use the discrete Fourier transform (DFT) matrix factorization based on the Kronecker product to express the family of radix rk single-path delay commutator/single-path delay feedback (SDC/SDF) pipeline fast Fourier transform (FFT) architectures. The matricial expressions of the radix r, r 2, r 3, and r 4 decimation-in-frequency (DIF) SDC/SDF pipeline architectures are derived. These expressions can be written using a small set of operators, resulting in a compact representation of the algorithms. The derived expressions are general in terms of r and the number of points of the FFT N. Expressions are given where it is not necessary that N is a power of rk. The proposed set of operators can be mapped to equivalent hardware circuits. Thus, the designer can easily go from the matricial representations to their implementations and vice versa. As an example, the mapping of the operators is shown for radix 2, 22, 23, and 24, and the details of the corresponding SDC/SDF pipeline FFT architectures are presented. Furthermore, a general expression is given for the SDC/SDF radix rk pipeline architectures when k > 4. This general expression helps the designer to efficiently handle a wider design exploration space and select the optimum single-path architecture for a given value of N.

Radix $r^{k} $ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

This paper presents the design and implementation of a pipeline radix-22 SDF FFT core for DVB-T/DVB-H receivers. DVB-T/DVB-H operation needs 2K/4K/8K multiple mode FFT processors. The necessary changes are introduced in the radix-22 SDF architecture to achieve an efficient FFT implementation. SNR and area results for different data and twiddle factor bitwidths are provided.

/pdf/an-fft-core-for-dvb-t-dvb-h-receivers-58nlcy53x5.pdf

An FFT Core for DVB-T/DVB-H Receivers

The mobile data traffic increase and the future connection of billions of Internet of Things (IoT) devices require operators to reshape the existing transport network architecture. Today, more than 50 % of Base-stations (BTS) are backhauled via radio. Radio technology can continue to play this vital role in future transport networks if it is able to evolve to cope with the new capacity level and latency requirements supporting the new 5G services. In this paper, a possible answer to this demand is provided, proposing a radio solution working in D-Band (130-170 GHz) and enabling a reconfigurable meshed network that can support the backhaul needs of future 5G and beyond networks.

D-Band Transport Solution to 5G and Beyond 5G Cellular Networks

In this paper we present an approach to simplify the design of IFFT/FFT cores for OFDM applications, A novel software tool is proposed, called AFORE. It is able to generate efficient single and multiple mode IFFT/FFT processors. AFORE employs a parallel architecture, where the degree of parallelism can be varied. This way, the tool can find a trade off between area and processing time to meet the system specification. In order to assess the quality of the proposed approach, results are provided for some of the most widely used OFDM standards, such as, WLAN 802.11a/g, WMAN 802.16a, DVB-T.

An approach to simplify the design of IFFT/FFT cores for OFDM systems

This paper presents the design of a wideband and high-linearity $E$ -band transmitter integrated in a 55-nm SiGe BiCMOS technology. It consists of a double-balanced bipolar ring mixer which upconverts a 16–21-GHz IF signal to the 71–76- and 81–86-GHz bands by the use of a 55/65-GHz local oscillator signal, followed by a broadband power amplifier which employs 2-way output power combining using an integrated low-loss balun transformer. The transmitter exhibits an average conversion gain of 24 dB and 22 dB at the 71–76- and 81–86-GHz bands, respectively, with an output 1-dB compression point greater than 14 and 11.5 dBm at each band. A maximum output power of 16.8 dBm is measured at 71 GHz. The dc power consumption is 575 mW. The presented transmitter is used to demonstrate the transmission of a 10.12-Gb/s 64 quadrature amplitude modulated signal with a spectral efficiency of 5.06 bit/s/Hz, which makes it suitable for use in future high-capacity backhaul and fronthaul point-to-point links.

Juan F. Sevillano

Papers

Radix $r^{k} $ FFTs: Matricial Representation and SDC/SDF Pipeline Implementation

An FFT Core for DVB-T/DVB-H Receivers

D-Band Transport Solution to 5G and Beyond 5G Cellular Networks

An approach to simplify the design of IFFT/FFT cores for OFDM systems

A Wideband and High-Linearity E -B and Transmitter Integrated in a 55-nm SiGe Technology for Backhaul Point-to-Point 10-Gb/s Links