Devices such as keyboards and touchscreens allow humans to communicate with machines. Neural interfaces, which can provide a direct, electrical bridge between analogue nervous systems and digital man-made systems, could provide a more efficient route to future information exchange. Here we review the development of electronic neural interfaces. The interfaces typically consist of three modules — a tissue interface, a sensing interface, and a neural signal processing unit — and based on technical milestones in the development of the electronic sensing interface, we group and analyse the interfaces in four generations: the patch clamp technique, multi-channel neural interfaces, implantable/wearable neural interfaces and integrated neural interfaces. We also consider key circuit and system challenges in the design of neural interfaces and explore the opportunities that arise with the latest technology This Review Article examines the development of neural interfaces, which can provide a direct, electrical bridge between analogue human nervous systems and digital man-made devices, considering challenges and opportunities created with such technology.

Electronic neural interfaces

This article presents a Gm-C-based continuous-time delta–sigma modulator (CTDSM) for artifact-tolerant neural recording interfaces. We propose the feedback-assisted Gm linearization technique, which is applied to the first Gm-C integrator by using a resistive feedback digital-to-analog converter (DAC) in parallel to the degeneration resistor of the input Gm. This enables the input Gm to process the quantization noise, thereby improving the input range and linearity of the Gm-C-based CTDSM, significantly. An energy-efficient second-order loop filter is realized by using a voltage-controlled oscillator (VCO) as the second integrator and a phase quantizer. A proportional–integral (PI) transfer function is employed at the first integrator, which minimizes the output swing while maintaining loop stability. Fabricated in a 110-nm CMOS process, the prototype CTDSM achieves a high input impedance, 300-mVpp linear input range, 80.4-dB signal-to-noise and distortion ratio (SNDR), 81-dB dynamic range (DR), and 76-dB common-mode rejection ratio (CMRR) and consumes only 6.5 $\mu \text{W}$ with a signal bandwidth of 10 kHz. This corresponds to a figure of merit (FoM) of 172.3 dB, which is the state of the art among the neural recording ADCs. This work is also validated through the in vivo experiment.

A 6.5- μ W 10-kHz BW 80.4-dB SNDR G m -C-Based CT ∆∑ Modulator With a Feedback-Assisted G m Linearization for Artifact-Tolerant Neural Recording

A single-chip, bidirectional brain–computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This article presents a prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel stimulus artifact cancellation. Stimulator power generation is integrated on a chip, providing ±11-V compliance from low-voltage supplies with a resonant charge pump. High-frequency (~3 GHz) self-resonant clocking is used to reduce the pumping capacitor area while suppressing the associated switching losses. A 32-tap least mean square (LMS)-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip occupies 4 mm2 in a 65-nm low power (LP) process and is powered by 2.5-/1.2-V supplies, dissipating $205~\mu \text{W}$ in recording and $142~\mu \text{W}$ in the stimulation and cancellation back-ends. The stimulation output drivers achieve 31% dc–dc efficiency at a maximum output power of 24 mW.

A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS

Increasing the efficiency of transmitters, as the largest consumers of energy, is relevant for any wireless communication devices. For higher efficiency, a number of methods are used, including envelope tracking and envelope elimination and restoration. Increasing the bandwidth of used frequencies requires expanding envelope modulators bandwidth up to 250–500 MHz or more. The possibility of using amplifiers with input signal quantization (AISQ), as an alternative to the most common hybrid envelope tracking modulators, is considered. An approach has been developed for optimizing AISQ characteristics according to the criterion of minimum loss when amplifying modern telecommunication signals with Rayleigh envelope distribution. The optimal quantization levels are determined and the energy characteristics of AISQ are calculated. AISQ loss power is shown to decrease by 1.66 times with two-level quantization, by 2.4 times with three-level quantization, and by a factor of 3.0–3.7 for four–five quantization levels compared to a class B amplifier. With these parameters, AISQ becomes competitive with respect to hybrid envelope tracking modulators but does not have electromagnetic interference from the pulse width modulation (PWM) path.

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Broadband and Efficient Envelope Amplifier for Envelope Elimination and Restoration/Envelope Tracking Higher-Efficiency Power Amplifiers

A simple, physically based analysis illustrate the noise processes in CMOS inverter-based and differential ring oscillators. A time-domain jitter calculation method is used to analyze the effects of white noise, while random VCO modulation most straightforwardly accounts for nicker (1/f) noise. Analysis shows that in differential ring oscillators, white noise in the differential pairs dominates the jitter and phase noise, whereas the phase noise due to flicker noise arises mainly from the tail current control circuit. This is validated by simulation and measurement. Straightforward expressions for period jitter and phase noise enable manual design of a ring oscillator to specifications, and guide the choice between ring and LC oscillator.

Phase noise and jitter in CMOS ring oscillators

The bidirectional neural interface is essential to realize the closed-loop neuromodulation, which is the core of next-generation neurological devices. For the bidirectional neural interface, a recording circuit with a high dynamic range (DR) is required to record the neural signal while stimulating the neuronal cells simultaneously. This article presents a voltage-controlled oscillator (VCO)-based neural-recording IC, which directly quantizes the input signal and achieves a large DR to process the small-amplitude neural signal in the presence of the large-amplitude stimulation artifact (SA). A feedback-controlled source degeneration is applied to the input transconductor circuit ( $G_{\mathrm {m, in}}$ ) by using a resistor digital-to-analog converter (R-DAC). It mitigates the circuit nonlinearity, resulting in a large signal-to-noise-and-distortion ratio (SNDR) and a high input impedance ( $Z_{\mathrm {in}}$ ). The implemented neural-recording IC achieves 81.3-dB SNDR over 200-Hz signal bandwidth and 200-mVpp maximum allowable input range with consuming 3.9 $\mu \text{W}$ per channel. The in-vitro measurement with prerecorded neural signal demonstrates that the original neural signal is well preserved in the presence of the large-amplitude artifact without any saturation or significant distortion.

A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface

In recent years, buck-boost converters have been widely utilized for battery-powered mobile systems such as RF power amplifiers, battery chargers, and LED drivers. However, in a wide battery voltage range, they face challenges including dynamic voltage scaling (DVS), wide load current range, and dynamic line/load transients while ensuring reliability for an industrial usage. To resolve these issues, the conventional buck-boost (CBB) converter should overcome the characteristic of discontinuity in the output transfer current (OTC) which causes degradation of loop dynamics and transient response. Several past works with continuous OTC have been proposed to resolve these problems, but their voltage conversion ratios are limited [1], [2]. Moreover, in [3], [4], a high-voltage (HV) process, which necessitates large active area and incurs high fabrication cost, is required to withstand voltage stresses over 10V (2×V IN ) applied across power switches. To overcome the above challenges, this paper proposes a voltage-tolerant three-level buck-boost (TLBB) converter. The TLBB has continuous OTC and uses only normal 5V CMOS devices for its switches. In addition, a voltage-tolerant dual channel-interleaved three-level buck-boost (DTLBB) converter is suggested for applications [5] requiring a wide range of load current and high conversion ratio while supporting fast DVS transition.

11.7 A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate

In the recent 3GPP standard, 5G New Radio (NR) in the sub-6GHz frequency band supports up to 100MHz bandwidth (BW) for uplink channel and requires fast on/off transition below $10 \mu \mathrm {s}$ to support short transition-time interval (TTI). Thus, it forces the supply modulator (SM) to track the NR-100MHz envelope signal for power saving of an RF power amplifier (RF-PA) and requires a fast dynamic voltage-scaling (DVS) transition. For the 3G/LTE uplink, the SM has to satisfy low receiver-band noise (RxBN) for LTE-FDD bands [1] and a boosted output for Power Class 2 high-power user equipment (HPUE) in TD-LTE [2], [3]. In order to support the 100MHz envelope tracking (ET) BW, the SM must have a 3dB bandwidth of at least 125MHz while keeping sufficient phase margin in the presence of few-hundred-pF load capacitance. Furthermore, a typical linear-assisted SM topology has maximum efficiency limitation due to the AB bias current, sinking- and sourcing-current of the linear amplifier. In this work, a voltage-buffer-compensated (VBC) Class-AB linear amplifier (LA) and a feed-forward fast-switching (FFFS) buck converter are proposed to achieve the 100MHz ET BW and high system-power efficiency.

15.1 An 88%-Efficiency Supply Modulator Achieving 1.08μs/V Fast Transition and 100MHz Envelope-Tracking Bandwidth for 5G New Radio RF Power Amplifier

Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 \Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.

33.9 A Hybrid Switching Supply Modulator Achieving 130MHz Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF Power Amplifiers

The capacitively coupled instrumentation amplifier (CCIA) is broadly used for neural signal acquisition. Although it is suitable for various biopotential recording applications, the CCIA is vulnerable to capacitor mismatches, which degrades the common-mode rejection ratio (CMRR). The neural signals with small amplitude can be easily contaminated by large-amplitude common-mode (CM) interferences due to the degraded CMRR. This brief presents a CMRR enhancement circuit for the CCIA, with which the capacitor mismatches can be compensated in a power-efficient manner. In the proposed CCIA, the gains of a pair of output stages are controlled separately to reject the output signals generated by the CM interferers in the presence of capacitor mismatches. Employing the proposed CMRR enhancement scheme, the implemented CCIA achieves a CMRR over 90 dB from 10 Hz to 1 kHz and 3.4- $\mu \text{V}_{\mathrm{ rms}}$ integrated input-referred noise (IRN) while only consuming $1.5~\mu \text{W}$ per channel.

Jun-Suk Bang

Papers

A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface

11.7 A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter with Continuous Transfer Current and Flying Capacitor Soft Charger Achieving 96.8% Power Efficiency and 0.87µs/V DVS Rate

15.1 An 88%-Efficiency Supply Modulator Achieving 1.08μs/V Fast Transition and 100MHz Envelope-Tracking Bandwidth for 5G New Radio RF Power Amplifier

33.9 A Hybrid Switching Supply Modulator Achieving 130MHz Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF Power Amplifiers

A CMRR Enhancement Circuit Employing Gₘ-Controllable Output Stages for Capacitively Coupled Instrumentation Amplifiers