Because of the simplicity of design and measurement, as well as the accuracy of results, the 2×-thru de-embedding has replaced the traditional de-embedding algorithms such as thru-reflect-line and short-open-load-thru for printed circuit board (PCB) characterization. In this paper, the theory of [$2^{n}$ -port 2×-Thru de-embedding is derived first. The self-error reduction schemes are introduced to mitigate the de-embedding errors due to non-ideal manufacturing effects that make mode conversion terms non-zero. Both the theory and the self-error reduction schemes are fully validated through simulation and measurement cases.

Multi-Ports ( [$2^{n}$ ) 2×-Thru De-Embedding: Theory, Validation, and Mode Conversion Characterization

The ball grid array (BGA) structure is the interconnection between package to printed circuit board and the discontinuity from BGA affects the performance for the whole link path in the high-speed digital system. So, it is important to accurately model the BGA structures. In current methods, the current distribution of conductors is treated as isotropic. However, the pitch size of solder balls is comparable to the diameter. The current is no longer uniformly distributed. In this paper, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3-D structure to 2-D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained in [1] . A $\pi $ topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full-wave simulation can be achieved up to 40 GHz.

Analytical Equivalent Circuit Modeling for BGA in High-Speed Package

S -parameter de-embedding methods require multiple fixtures to be identical. However, due to manufacturing variations, the fixtures are never perfectly identical, which violates the assumptions for the de-embedding algorithms and, in turn, introduces errors. In this article, a novel methodology is proposed to estimate the errors due to de-embedding for practical transmission line measurements. The circuit models of the thru and total lines with fixtures are created. Perturbation in the fixtures is introduced based on the fixture variation estimated by time-domain reflectometry measurements. The method can predict the envelope and estimate the confidence interval of the de-embedded insertion loss using a limited number of simulation cases.

https://ieeexplore.ieee.org/ielam/15/9166805/9104863-aam.pdf

S -Parameter De-Embedding Error Estimation Based on the Statistical Circuit Models of Fixtures

Far-end crosstalk (FEXT) noise is one of the major issues that limits signal integrity performance for high-speed digital products. It is important to estimate the crosstalk noise accurately to avoid noise margin failure or overdesigned transmission lines. Traditionally, analytical formulas for crosstalk noise are based on lossless and perfect impedance match assumptions, which provide limited guidance for a practical high-speed transmission line design. A phenomenon is observed that a lossy conductor increases the FEXT on coupled striplines. To provide a reasonable explanation, analytical and numerical investigations were performed using a modal analysis based approach. A new FEXT component due to the lossy conductor is proposed. Such FEXT component is important to a high-speed stripline design because it is a major contributor when all terminals are matched. To estimate the impact of loss on FEXT, a practical and fast estimation approach is proposed.

Comprehensive and Practical Way to Look at Far-End Crosstalk for Transmission Lines With Lossy Conductor and Dielectric

Crosstalk noise on the printed circuit board is usually decreased by adding shielding ground (GND). In the trace routing area, the shielding vias are added to isolate the coupling between different traces. In the ball gate array (BGA) and pin field area, assigning more GND pins has demonstrated the effectiveness of crosstalk reduction between signals. However, such design decreases the signal to ground (S:G) ratio dramatically, herein, it is not suitable for applications that require high signal pin density. Unlike the treatment in the conventional methodology, in this paper, the differential crosstalk is mitigated by using the principle of symmetry on two adjacent differential signal pairs in the BGA and pin field regions. New full pin map patterns are proposed and compared with the conventional full pin map patterns. Without sacrificing the S:G ratio, the proposed maps prove the superiority in mitigating both differential far-end and near-end integrated crosstalk noise. To maintain the low crosstalk level in the entire link path, guidance of differential trace routing is provided and demonstrated in the details. All models in this paper satisfy SerDes channel designing and manufacturing requirements.

Differential Crosstalk Mitigation in the Pin Field Area of SerDes Channel With Trace Routing Guidance

The integrated crosstalk noise (ICN) has been widely used as an alternative to the insertion crosstalk ratio (ICR) for channel crosstalk evaluation in the IEEE 802.3ba standard. In this work, the differential ICN mitigation scheme by using idea of orthogonality is implemented in two adjacent differential pairs first. In the full pin map area of SerDes channel, new pin map patterns based on such scheme are prosed and compared with the conventional pan map patterns. The new pin maps mitigate the differential ICN drastically, yet maintain the G:s ratio. A preliminary study is conducted on fan-out trace routing to maintain the benefit from new pin map patterns.

Differential Integrated Crosstalk Noise (ICN) Mitigation in the Pin Field Area of SerDes Channel

With an increased data rate of high-speed PCBs, an increase in crosstalk degrades the signal integrity of the highspeed system. In most PCB designs, via-to-via coupling has the largest impact on crosstalk. Until now, multiple PCB design methods for crosstalk mitigation are proposed under the IC pin field area, such as increasing the distance between signal pairs, adding more ground vias in between the signal vias and placing signal pairs orthogonal to each other. However, such methods sacrifice the signal to ground (S:G) ratio and require a change in the IC package ball map. In this paper, two different via designs are proposed to reduce crosstalk without sacrificing the S:G ratio, while maintaining the package ball maps. In the first proposed design, crosstalk is mitigated through tilted drilling, where the vias are drilled with 45 degrees angle on the PCB. Differential via pairs located in different rows achieves orthogonality for crosstalk cancellation when viewed from the horizontal cross-section. In the second proposed design, additional intermediate vias are designed to achieve orthogonality between differential via pairs without changing the IC package ball map or the drilling direction. Using a 3D full-wave simulation tool, the two prosed designs are simulated. Simulation results demonstrate that both designs decrease in crosstalk with negligible change in insertion loss and return loss compared to the conventional via design up to 30 GHz range. The proposed methods can be directly applied to lower the crosstalk in the existing high-speed PCBs with minor adjustments in the PCB design while maintaining the same IC packages.

Differential Via Designs for Crosstalk Reduction in High-Speed PCBs

The integrated crosstalk noise (ICN) has been wildly used as an alternative to the insertion crosstalk ratio (ICR) for channel crosstalk evaluation in the IEEE 802.3ba standard. In this work, a differential ICN analysis is performed for several configurations of package-to-PCB transitions. Using the design of experiment (DoE) statistical method, differential ICN is quickly estimated for various input factors such as pin mapping, physical dimensions, and level of shielding. Optimization guide line is proposed to maintain the tradeoff among the differential ICN, design space, and manufacturing cost.

Junda Wang

Papers

Differential Crosstalk Mitigation in the Pin Field Area of SerDes Channel With Trace Routing Guidance

Differential Integrated Crosstalk Noise (ICN) Mitigation in the Pin Field Area of SerDes Channel

Differential Via Designs for Crosstalk Reduction in High-Speed PCBs

Differential integrated crosstalk noise (ICN) reduction among multiple differential BGA and Via pairs by using design of experiments (DoE) method