抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Recurrent Neural Networks (RNNs) are a class of machine learning algorithms used for applications with time-series and sequential data. Recently, there has been a strong interest in executing RNNs on embedded devices. However, difficulties have arisen because RNN requires high computational capability and a large memory space. In this paper, we review existing implementations of RNN models on embedded platforms and discuss the methods adopted to overcome the limitations of embedded systems. We will define the objectives of mapping RNN algorithms on embedded platforms and the challenges facing their realization. Then, we explain the components of RNN models from an implementation perspective. We also discuss the optimizations applied to RNNs to run efficiently on embedded platforms. Finally, we compare the defined objectives with the implementations and highlight some open research questions and aspects currently not addressed for embedded RNNs. Overall, applying algorithmic optimizations to RNN models and decreasing the memory access overhead is vital to obtain high efficiency. To further increase the implementation efficiency, we point up the more promising optimizations that could be applied in future research. Additionally, this article observes that high performance has been targeted by many implementations, while flexibility has, as yet, been attempted less often. Thus, the article provides some guidelines for RNN hardware designers to support flexibility in a better manner.

Recurrent Neural Networks: An Embedded Computing Perspective

A Survey of Spintronic Architectures for Processing-in-Memory and Neural Networks

Traditional TEM-based I/O communication through either PCB traces or free space has significant path loss and electromagnetic (EM) interferences that are hardly employed toward low-power and dense I/Os for data server. We propose a 0.1–1 THz or sub-terahertz (THz) I/O interface using surface plasmonic polariton (SPP) interconnects in CMOS to obtain high-energy efficiency and low-crosstalk interconnect. The surface wave can be established with on-chip generation and further deployed for signal propagation by corrugating periodical grooves onto the traditional transmission line. It will result in a strongly localized electromagnetically wave onto the surface of top-layer metal in wideband, leading to the broadband low EM coupling between many core and memories. Moreover, we have also developed a high on/off ratio split-ring-resonator-based modulator to support the sub-THz I/O communication. The proposed SPP interconnect achieves data rate of 25 Gb/s with 0.016 pJ/b/mm energy efficiency at 140 GHz in 65-nm CMOS. In addition, two surface-wave channels placed with 2.4- $\mu \text{m}$ spacing exhibits an average −28-dB crosstalk ratio.

An Energy-Efficient and Low-Crosstalk Sub-THz I/O by Surface Plasmonic Polariton Interconnect in CMOS

An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology.

/pdf/on-chip-sub-terahertz-surface-plasmon-polariton-transmission-533tjs1wy6.pdf

On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.

Image processing in conventional logic-memory I/O-integrated systems will incur significant communication congestion at memory I/Os for excessive big image data at exa-scale. This paper explores an in-memory machine learning on neural network architecture by utilizing the newly introduced domain-wall nanowire, called DW-NN. We show that all operations involved in machine learning on neural network can be mapped to a logic-in-memory architecture by non-volatile domain-wall nanowire. Domain-wall nanowire based logic is customized for in machine learning within image data storage. As such, both neural network training and processing can be performed locally within the memory. The experimental results show that system throughput in DW-NN is improved by 11.6x and the energy efficiency is improved by 92x when compared to conventional image processing system.

/pdf/energy-efficient-in-memory-machine-learning-for-data-1sxzzl47cr.pdf

Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory

Two novel metamaterial devices including Split Ring Resonator (SRR) modulator and Surface Plasmon Polariton (SPP) interconnect (including SPP T-line and coupler) are proposed with CMOS on-chip integration operated at 140GHz. By introducing sub-wavelength periodical corrugation structure onto T-line, SPP is established to propagate signals with strongly localized surface wave, which results in low crosstalk between two back-to-back placed SPP T-lines. Moreover, by stacking two SRR unit-cells with opposite placement, the SRR based modulator manifests itself as a magnetic metamaterial achieving significant reduction of radiation loss with 23dB extinction ratio at sub-THz. As explored in 65nm CMOS, the proposed surface-wave interconnects and SRR modulator have shown great potential for future sub-THz wireline communication in CMOS.

CMOS sub-THz on-chip communication with SRR modulator and SPP interconnect

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Memory device, and data processing method based on multi-layer RRAM crossbar array

Data analytics such as face recognition involves large volume of image data, and hence leads to grand challenge on mobile platform design with strict power requirement. Emerging non-volatile STT-MRAM has the minimum leakage power and comparable speed to SRAM, and hence is considered as a promising candidate for data-oriented mobile computing. However, there exists significantly higher write-energy for STT-MRAM when compared to the SRAM. Based on the use of STT-MRAM, this paper introduces an energy-efficient non-volatile in-memory accelerator for a sparse-representation based face recognition algorithm. We find that by projecting high-dimension image data to much lower dimension, the current scaling for STT-MRAM write operation can be applied aggressively, which leads to significant power reduction yet maintains quality-of-service for face recognition. Specifically, compared to a baseline with SRAM, leakage power and dynamic power are reduced by 91.4% and 79% respectively with only slight compromise on recognition rate.

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition

An image recognition accelerator (20), a terminal device and an image recognition method. The image recognition accelerator (20) comprises a dimension reduction processing module (205), an NVM (210) and an image matching module (215). In a process where the image recognition accelerator (20) performs image recognition, firstly, the dimension reduction processing module (205) reduces the dimension of first image data according to a set dimension reduction parameter γ. The NVM (210) writes a low ω bit of each numerical value in the first image data after the dimension reduction into a first storage region (2104) of the NVM (210) according to a set first current I, and writes a high N-ω bit of each numerical value in the first image data after the dimension reduction into a second storage region (2106) of the NVM (210) according to a set second current, wherein the first current is less than the second current. Thus, the matching module (215) can determine whether an image library stored in the NVM contains image data matching the first image data after the dimension reduction. The image recognition accelerator (20) can ensure the accuracy of image recognition on the basis of reducing the system power consumption of a terminal device.

Junfeng Zhao

Papers

Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory

CMOS sub-THz on-chip communication with SRR modulator and SPP interconnect

Memory device, and data processing method based on multi-layer RRAM crossbar array

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition

Image recognition accelerator, terminal device and image recognition method