Preparing the books to read every day is enjoyable for many people. However, there are still many people who also don't like reading. This is a problem. But, when you can support others to start reading, it will be better. One of the books that can be recommended for new readers is computer aided analysis of electronic circuits algorithms and computational techniques. This book is not kind of difficult book to read. It can be read and understand by the new readers.

Computer-aided analysis of electronic circuits: Algorithms and computational techniques

Memristor-based memory

This paper presents a SPICE model for memristive devices. It builds on existing models and is correlated against several published device characterization data with an average error of 6.04%. When compared to existing alternatives, the proposed model can more accurately simulate a wide range of published memristors. The model is also tested in large circuits with up to 256 memristors, and was less likely to cause convergence errors when compared to other models. We show that the model can be used to study the impact of memristive device variation within a circuit. We examine the impact of nonuniformity in device state variable dynamics and conductivity on individual memristors as well as a four memristor read/write circuit. These studies show that the model can be used to predict how variation in a memristor wafer may impact circuit performance.

Generalized Memristive Device SPICE Model and its Application in Circuit Design

Efficient amplification of spoof surface plasmon polaritons (SPPs) is proposed at microwave frequencies by using a subwavelength-scale amplifier For this purpose, a special plasmonic waveguide composed of two ultrathin corrugated metallic strips on top and bottom surfaces of a dielectric substrate with mirror symmetry is presented, which is easy to integrate with the amplifier It is shown that spoof SPPs are able to propagate on the plasmonic waveguide in broadband with low loss and strong subwavelength effect By loading a low-noise amplifier chip produced by the semiconductor technology, the first experiment is demonstrated to amplify spoof SPPs at microwave frequencies (from 6 to 20GHz) with high gain (around 20dB), which can be directly used as a SPP amplifier device The features of strong field confinement, high efficiency, broadband operation, and significant amplification of the spoof SPPs may advance a big step towards other active SPP components and integrated circuits

Broadband amplification of spoof surface plasmon polaritons at microwave frequencies

The practical deployment of massive multiple-input multiple-output (MIMO) in future fifth generation (5G) wireless communication systems is challenging due to its high hardware cost and power consumption. One promising solution to address this challenge is to adopt the low-resolution analog-to-digital converter (ADC) architecture. However, the practical implementation of such architecture is challenging due to the required complex signal processing to compensate the coarse quantization caused by low-resolution ADCs. Therefore, few high-resolution ADCs are reserved in the recently proposed mixed-ADC architecture to enable low-complexity transceiver algorithms. In contrast to previous works over Rayleigh fading channels, we investigate the performance of mixed-ADC massive MIMO systems over the Rician fading channel, which is more general for the 5G scenarios like Internet of Things (IoT). Specially, novel closed-form approximate expressions for the uplink achievable rate are derived for both cases of perfect and imperfect channel state information (CSI). With the increasing Rician $K$-factor, the derived results show that the achievable rate will converge to a fixed value. We also obtain the power-scaling law that the transmit power of each user can be scaled down proportionally to the inverse of the number of base station (BS) antennas for both perfect and imperfect CSI. Moreover, we reveal the trade-off between the achievable rate and energy efficiency with respect to key system parameters including the quantization bits, number of BS antennas, Rician $K$-factor, user transmit power, and CSI quality. Finally, numerical results are provided to show that the mixed-ADC architecture can achieve a better energy-rate trade-off compared with the ideal infinite-resolution and low-resolution ADC architectures.

Performance Analysis of Mixed-ADC Massive MIMO Systems over Rician Fading Channels

Design of hybrid circuits and systems based on CMOS and nano-device requires rethinking of fundamental circuit analysis to aid design exploration. Conventional circuit analysis with modified nodal analysis (MNA) cannot consider new nano-devices such as memristor together with the traditional CMOS devices. This paper has introduced a new MNA method with magnetic flux (Φ) as new state variable. New SPICE-like circuit simulator is thereby developed for the design of hybrid CMOS and memristor circuits. A number of CMOS and memristor-based designs are explored, such as oscillator, chaotic circuit, programmable logic, analog-learning circuit, and crossbar memory, where their functionality, performance, reliability and power can be efficiently verified by the newly developed simulator. Specifically, one new 3-D-crossbar architecture with diode-added memristor is also proposed to improve integration density and to avoid sneak path during read-write operation.

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Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis

To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of ±8.2 dB ( -90.2 to -106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of ±2.5 dB ( -105.9 to -110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz.

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Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer

Hybrid integration of CMOS and nonvolatile memory (NVM) devices has become the foundation for emerging nonvolatile memory-based computing. The primary challenge to validate hybrid memory system with both CMOS and NVM devices is to develop a SPICE-like simulator that can simulate the dynamic behavior accurately and efficiently. Since memristor, spin-transfer-toque magnetic-tunneling-junction (STT-MTJ) and phase-change-memory (PCM) devices are the most promising candidates of next generation of NVM devices, it is under great interest in including these new devices in the standard CMOS design flow. The previous approaches either ignore dynamic effect without consideration of internal states for dynamic behavior, or need complex equivalent circuits to represent those devices. This paper proposes a new modified nodal analysis for NVM devices with identified internal state variables for dynamic behavior. As such, compact SPICE-like implementation can be derived for all three new NVM devices in the design of large-scale memory circuits. As demonstrated by a number of examples on hybrid memory circuits with both CMOS and NVM devices, our newly developed SPICE-like simulator can capture dynamic behaviors of memristor, STT-MTJ and PCM devices, and can also reduce CPU runtime by 20-69 times when compared to the previous equivalent circuit based approaches.

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Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

Based on a newly introduced zero phase shifter (ZPS), a 2-D distributed power-combining network is developed in this paper to provide simultaneous distributed amplification and power combining. One type of metamaterial, called the composite right/left-handed transmission line, is deployed to design ZPS with detailed considerations to achieve low loss and wideband performance. The proposed 2-D distributed power combining is implemented for one 60-GHz power amplifier (PA) design by a UMC standard 65-nm CMOS process. Measured results show that the fabricated PA has 0.39- mm2 area, 8.3-dB gain, 7.1% power-added efficiency, and 9.7-dBm P1 dB with 16-GHz bandwidth (44-60 GHz).

/pdf/a-2-d-distributed-power-combining-by-metamaterial-based-zero-4w47obtxkz.pdf

A 2-D Distributed Power Combining by Metamaterial-Based Zero Phase Shifter for 60-GHz Power Amplifier in 65-nm CMOS

Image processing in conventional logic-memory I/O-integrated systems will incur significant communication congestion at memory I/Os for excessive big image data at exa-scale. This paper explores an in-memory machine learning on neural network architecture by utilizing the newly introduced domain-wall nanowire, called DW-NN. We show that all operations involved in machine learning on neural network can be mapped to a logic-in-memory architecture by non-volatile domain-wall nanowire. Domain-wall nanowire based logic is customized for in machine learning within image data storage. As such, both neural network training and processing can be performed locally within the memory. The experimental results show that system throughput in DW-NN is improved by 11.6x and the energy efficiency is improved by 92x when compared to conventional image processing system.

/pdf/energy-efficient-in-memory-machine-learning-for-data-1sxzzl47cr.pdf

Wei Fei

Papers

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer

Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

A 2-D Distributed Power Combining by Metamaterial-Based Zero Phase Shifter for 60-GHz Power Amplifier in 65-nm CMOS

Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory