Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.

What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

This work details the harmful effect of parasitic resistances and capacitances on RF figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) FD SOI n-MOSFETs. It is demonstrated that intrinsically, UTBB device can reach very high cut-off frequency (fT) provided the reduction of parasitic elements. In addition, based on device simulation, we demonstrate that with appropriate configuration, Asymmetric Double Gate (ADG) regime provides a slight improvement of RF figures-of-merit.

Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit

Provided are a semiconductor device capable of satisfactorily solving a floating-body problem and a hot carrier problem which often arise in an SOI device and of causing a widely distributed partial isolating film to generate a crystal defect for peripheral structures with difficulty and a method of manufacturing the semiconductor device. A dummy region DM 1 having no function as an element is formed at almost regular intervals in a partial isolating film 5 b provided between MOS transistors TR 1 . Consequently, the occupation rate of the dummy region DM 1 having a lower resistance value than that of a silicon layer 3 b provided under the partial isolating film 5 b is increased so that the floating-body problem and the hot carrier problem can be solved.

Semiconductor device, method of manufacturing the same and method of arranging dummy region

The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. It is shown that although nanoscale FinFETs achieve higher values of intrinsic dc gain (nearly 20 dB higher than planar SG devices), they also present higher gate capacitance that severely undermines their rf performance. We also show that at large values of drain currents, well-designed conventional planar single and double gate SOI MOSFETs attain higher values of cut-off frequency compared to FinFETs, whereas at lower drain currents, a well-aligned planar double gate SOI MOSFET is the optimal structure. The reason for higher parasitic capacitance in FinFETs as compared to planar MOSFETs is examined in detail. An assessment of the impact of back gate misalignment on the rf performance of a 25 nm gate length planar double gate MOSFET indicates that a misalignment of 12 nm towards the source end is acceptable to give superior performance to a FinFET. The importance of source/drain extension region engineering in nanoscale FinFETs for ultra-low voltage analogue applications is also investigated. RF figures of merit for planar and vertical MOS devices are also compared based on layout-area calculations. The paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical MOSFETs.

https://iopscience.iop.org/article/10.1088/0268-1242/22/5/005/pdf

Comparative analysis of nanoscale MOS device architectures for RF applications

Device simulation of the 180-, 90-, and 65-nm CMOS generations shows that in NMOSTs, the cut-off frequency f/sub T/ and the maximum oscillation frequency f/sub max/ are roughly inversely proportional to the gate length. The voltage-gain bandwidth f/sub A/ depends only weakly on the gate length. At 40-nm gate length, f/sub T/ values of 300 GHz are predicted. For small values of the drain and source contact resistance (<10/sup -8/ /spl Omega//spl middot/cm/sup 2/), f/sub T/ can only be improved by a further reduction of the gate length. The f/sub max/ values (for zero gate resistance higher than f/sub T/) degrade strongly with increasing gate resistance. Simple approximate formulas for the dependence of f/sub T/ and f/sub A/ on the contact resistances are presented.

Scaling of characteristic frequencies in RF CMOS

We achieved 135 GHz f/sub max/ and 1098 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide The suppression of V/sub th/ variations was also realized due to this structure Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 /spl mu/m floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V/sub th/) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V/sub th/-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 /spl mu/m, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current.

K. Eikyu

Papers

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 /spl mu/m partially depleted SOI MOSFETs

Clarification of Floating-Body Effects on Current Drivability in Deep Sub-Quarter Micron Partially-Depleted SOI MOSFET's