S. Maegawa

TL;DR: In this article, the substrate bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated.

TL;DR: In this paper, a partial trench isolation (PTI) technique is proposed to eliminate floating body effects while maintaining SOI-inherent merits and can realize scalable deep sub-quarter micron LSIs using accumulated bulk-design properties without layout modification.

TL;DR: In this article, the authors proposed a 0.18/spl mu/m SOI CMOS using hybrid trench isolation with high resistivity substrates (HRS) and reveal its impact on high performance embedded RF/analog applications, which is essential for "system on a chip (SOC)".

TL;DR: In this paper, a 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated.

TL;DR: In this paper, the authors achieved 135 GHz f/sub max/ and 1098 dB MSG at 40 GHz using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide.