An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Switch Circuit and Method of Switching Radio Frequency Signals

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of low-voltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, VT, and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

Review and future prospects of low-voltage RAM circuits

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.

Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device

SOI-DRAM is expected to have long data retention time because the data leakage path is limited only through a cell transistor. High speed low power operation is realized due to reduced junction capacitances. Moreover, since the capacitance ratio Cb/Cs is reduced, the read out signal amplitude increases. For these reasons SOI is well suited to low power supply voltage DRAMs. However, because SOI uses body-floating transistors for memory cells, there is a possibility that majority carriers within the floating body can cause problems. To date, only the static data retention characteristics have been reported, with nothing written about the dynamic data retention characteristics for full DRAM operation. This paper details the results of an analysis of the floating body caused leakage mechanism and its effect on dynamic data retention. A proposal is made to obtain superior dynamic data retention time.

Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, "substrate bias" is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits.

Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

0.6- mu m CMOS technologies were developed on thin SIMOX film and applied to a 16 K gate CMOS gate array. High-speed operation with low power consumption characteristics was verified with ring oscillators on the thin SOI CMOS gate array with V/sub D/=3 V, compared with bulk-Si ring oscillators with the same dimension. Parasitic capacitances in thin SOI and bulk-Si circuits were estimated to clarify the origin of the speed gain from the propagation delay times of the ring oscillators with various kinds of controlled load capacitances. Full functional operation was achieved for a 16 b*16 b multiplier on the SOI CMOS gate array with 1.4 times higher speed operation and 0.8 times lower power consumption than the multiplier on a bulk-Si substrate. >

A high speed 0.6- mu m 16 K CMOS gate array on a thin SIMOX film

This paper has reported a Ka-band (27-40GHz) high efficiency doherty power amplifier (DPA) MMIC (Monolithic Microwave Integrated Circuit) using GaN-HEMT for 5G application. To realize a high power and high efficiency DPA in Ka-band, a parasitic output capacitance (C ds ) is compensated by shunt inductor through resonance using high accuracy large-signal model. As a result, the fabricated 2-stage DPA using GaN-HEMT achieves a measured saturation output power of 35.6dBm (3.6W) and peak PAE of 25.5%. PAE of 22.7% and 19.5% are obtained at 6dB and 8dB back-off, respectively. In addition, the measured ACLR is −25/−27dBc and PAE is 20.5% at average output power of 27.6dBm under 100MHz 64QAM modulated signal. To the best of author’s knowledge, the developed DPA is state-of-the art 5G amplifier at Ka-band.

A Ka-Band High Efficiency Doherty Power Amplifier MMIC using GaN-HEMT for 5G Application

This paper reports a 20 W Ka-band GaN high power MMIC (Monolithic Microwave Integrated Circuit) amplifier under continuous wave (CW) operation. The one-finger large signal models were made to take account of both the phase difference of RF gate voltage at a gate feeder and thermal effect. By using this model, the gate pitch length of unit cell transistor was optimally designed to obtain maximum output power as MMIC amplifier under CW operation. As a result, 21.7W output power under CW operation was successfully achieved with power added efficiency (PAE) of 19.8% at Ka-band by a single-ended MMIC. To the best of authors' knowledge, this output power is state-of-the-art for GaN MMIC amplifiers under CW operation at Ka-band.

Yutaro Yamaguchi

Papers

Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM

Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

A high speed 0.6- mu m 16 K CMOS gate array on a thin SIMOX film

A Ka-Band High Efficiency Doherty Power Amplifier MMIC using GaN-HEMT for 5G Application

A CW 20W Ka-band GaN high power MMIC amplifier with a gate pitch designed by using one-finger large signal models