Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 /spl mu/m/spl times/0.75 /spl mu/m, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n/sup +/ polysilicon gates subjected to RTA at 1050/spl deg/C for 20 s and furnace annealing at 850/spl deg/C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications.

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Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

The boron penetration effect was compared for p/sup +/ poly gate PMOSFETs with pure oxide gates and nitrided oxide gates. For a gate thickness of 6.5 nm, reduced boron dosage and rapid thermal processing solve the problem of boron penetration in the pure oxide case. However, when the film thickness is less than 6.5 nm, only a nitrided oxide film can solve the problem. From the results of EDX analysis in nitrided oxide films, it was found that nitrogen build-up at the interface is small and that a nitrogen concentration of only a few percent leads to complete suppression of boron penetration down to the 2 nm range of film thickness. Excellent characteristics in 2.6 nm nitrided oxide gate p-MOSFETs, free from boron penetration effects, were demonstrated. >

Effects of boron penetration and resultant limitations in ultra thin pure-oxide and nitrided-oxide gate-films

The ability of thin reoxidized nitrided oxide (ONO) gate dielectrics formed by rapid thermal processing to act as a barrier to boron penetration resulting from p/sup +/ poly gate processing are investigated. Measurements comparing the threshold voltage instability of capacitors fabricated with BF/sub 2/ implanted poly gates subjected to various postgate thermal cycles have been performed. The ONO gate dielectrics are found to be an excellent impurity barrier to boron diffusion, even in the presence of fluorine. The extent of the nitridation is also found to affect the diffusion barrier properties, with the highest temperature nitridations forming the best barriers. Reoxidation of the nitrided films reduces the barrier properties somewhat, but improvement is still observed over SiO/sub 2/. >

Impurity barrier properties of reoxidized nitrided oxide films for use with P/sup +/-doped polysilicon gates

The combined effect of boron penetration and fluorine transport from P/sup +/ polycrystalline gates on flat-band voltage is studied. The SIMS concentration depth profiles elucidate the effect of annealing temperature on the fluorine transport, which in turn affects the boron penetration induced change in flat-band voltage. The fluorine diffusion in the poly gate is dominated by grain boundary diffusion. The identification of this mechanism is supported by SIMS profiles and a simulation based on a new methodology of network diffusion. >

Fluorine diffusion on a polysilicon grain boundary network in relation to boron penetration from P/sup +/ gates

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift. >

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p/sup +/-gate p-channel MOSFETs with fluorine incorporation

A study of the effects of P+ poly gate microstructure and gate oxide cycle on boron penetration from gate electrode through thin oxide is reported. The boron diffusion and the trap generation in the oxide can be significantly reduced by using an as-deposited amorphous Si gate and an oxide cycle which incorporates less Cl into the film. A strong interaction between fluorine and boron results in boron penetration into the channel and electron trap generation in the oxide. A larger grain size means fewer grain boundaries are available for boron and fluorine diffusion from the P+ gate to oxide. Less fluorine in the oxide results in less electron trap generation and less boron penetration to the Si substrate. A smaller content of Cl in the oxide results in a reduction of boron penetration. Finally, a co-implant of boron and fluorine into the as-deposited amorphous Si gate results in minimum boron diffusion into the Si substrate, which may provide the control of fluorine dose needed to reduce the interface trap density between oxide/Si interface. Increasing the grain size of the poly gate as reported above can be applied to reduce the large concentration of fluorine introduced into the gate oxide by other processes such as CVD tungsten polycide technology

K. Evans

Papers

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p/sup +/-gate p-channel MOSFETs with fluorine incorporation

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF 2 implanted P+ gate p-channel MOSFETs