We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

/pdf/a-double-tail-latch-type-voltage-sense-amplifier-with-18ps-aluyuprtro.pdf

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

With the rise of many-core chips that require substantial bandwidth from the network on chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects While numerous opto-electronic NoCs have been proposed, evaluations of photonic architectures have thus-far had to use a number of simplifications, reflecting the need for a modeling tool that accurately captures the tradeoffs for the emerging technology and its impacts on the overall network In this paper, we present DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks We explain our modeling framework and perform an energy-driven case study, focusing on electrical technology scaling, photonic parameters, and thermal tuning Our results show the implications of different technology scenarios and, in particular, the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature

/pdf/dsent-a-tool-connecting-emerging-photonics-with-electronics-36kgq89po0.pdf

DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling

Increasing integrated-circuit pin bandwidth has motivateda corresponding increase in the degree or radix of interconnection networksand their routers. This paper introduces the flattened butterfly, a cost-efficient topology for high-radix networks. On benign (load-balanced) traffic, the flattened butterfly approaches the cost/performance of a butterfly network and has roughly half the cost of a comparable performance Clos network.The advantage over the Clos is achieved by eliminating redundant hopswhen they are not needed for load balance. On adversarial traffic, the flattened butterfly matches the cost/performance of a folded-Clos network and provides an order of magnitude better performance than a conventional butterfly.In this case, global adaptive routing is used to switchthe flattened butterfly from minimal to non-minimal routing - usingredundant hops only when they are needed. Minimal and non-minimal, oblivious and adaptive routing algorithms are evaluated on the flattened butterfly.We show that load-balancing adversarial traffic requires non-minimalglobally-adaptive routing and show that sequential allocators are required to avoid transient load imbalance when using adaptive routing algorithms.We also compare the cost of the flattened butterfly to folded-Clos, hypercube,and butterfly networks with identical capacityand show that the flattened butterfly is more cost-efficient thanfolded-Clos and hypercube topologies.

/pdf/flattened-butterfly-a-cost-efficient-topology-for-high-radix-46tduypx6i.pdf

Flattened butterfly: a cost-efficient topology for high-radix networks

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

A 27-mW 3.6-gb/s I/O transceiver

The resolution of a comparator is determined by the dc input offset and the ac noise. For mixed-mode applications with significant digital switching, input-referred supply noise can be a significant source of error. This paper proposes an offset compensation technique that can simultaneously minimize input-referred supply noise. Demonstrated with digital offset compensation, this scheme reduces input-referred supply noise to a small fraction (13%) of one least significant bit (LSB) digital offset. In addition, the same analysis can be applied to analog offset compensation.

Offset compensation in comparators with minimum input-referred supply noise

This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.

A 27-mW 3.6-Gb/s I/O transceiver

A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10-12 with 231-1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.

K.-L.J. Wong

Papers

A 27-mW 3.6-gb/s I/O transceiver

Offset compensation in comparators with minimum input-referred supply noise

A 27-mW 3.6-Gb/s I/O transceiver

A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

A 10-mW 3.6-Gbps I/O transmitter