Journal ArticleDOI
Offset compensation in comparators with minimum input-referred supply noise
K.-L.J. Wong,Chih-Kong Ken Yang +1 more
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TLDR
In this article, an offset compensation technique that can simultaneously minimize input-referred supply noise was proposed to reduce the resolution of a comparator by the dc input offset and the ac noise.Abstract:
The resolution of a comparator is determined by the dc input offset and the ac noise. For mixed-mode applications with significant digital switching, input-referred supply noise can be a significant source of error. This paper proposes an offset compensation technique that can simultaneously minimize input-referred supply noise. Demonstrated with digital offset compensation, this scheme reduces input-referred supply noise to a small fraction (13%) of one least significant bit (LSB) digital offset. In addition, the same analysis can be applied to analog offset compensation.read more
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Proceedings ArticleDOI
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Journal ArticleDOI
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration
Manar El-Chammas,Boris Murmann +1 more
TL;DR: A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS to improve dynamic performance, and comparator offset calibration to reduce power dissipation.
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS : Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution
TL;DR: New techniques for logic circuits and interconnect, for memory, and for clock and power distribution are discussed, and the role of geometrically regular circuits as one promising solution is discussed.
Journal ArticleDOI
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS
TL;DR: In this article, the authors present a survey of recent computer-aided design efforts in modeling, analysis, and optimization for nanoscale designs with ever increasing amounts of statistical variation.
Journal ArticleDOI
A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V
Bernhard Goll,Horst Zimmermann +1 more
TL;DR: A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage Vt ap 0.4 V were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.65-V supply.
References
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Journal ArticleDOI
Matching properties of MOS transistors
TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Journal ArticleDOI
A 12-b 5-Msample/s two-step CMOS A/D converter
Behzad Razavi,Bruce A. Wooley +1 more
TL;DR: In this paper, the authors describe a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1- mu m CMOS technology.
Proceedings ArticleDOI
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link
TL;DR: A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link.
A 12-b 5-MSamplels Two-step CMOS AID Converter
Behzad Razavi,Bruce A. Wooley +1 more
TL;DR: The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1- mu m CMOS technology.
Proceedings ArticleDOI
A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation
TL;DR: The 4 Gb/s transceiver described in this paper achieves low power and low area using an input-multiplexed transmitter architecture, a regulated CMOS inverter-based delay-locked loop (DLL), and receiver offset calibration.