Resistive switching memories (RRAMs) are attractive for replacement of conventional flash in the future. Although different switching materials have been reported; however, low-current operated devices (<100 μA) are necessary for productive RRAM applications. Therefore, TaOx is one of the prospective switching materials because of two stable phases of TaO2 and Ta2O5, which can also control the stable low- and high-resistance states. Long program/erase endurance and data retention at high temperature under low-current operation are also reported in published literature. So far, bilayered TaOx with inert electrodes (Pt and/or Ir) or single layer TaOx with semi-reactive electrodes (W and Ti/W or Ta/Pt) is proposed for real RRAM applications. It is found that the memory characteristics at current compliance (CC) of 80 μA is acceptable for real application; however, data are becoming worst at CC of 10 μA. Therefore, it is very challenging to reduce the operation current (few microampere) of the RRAM devices. This study investigates the switching mode, mechanism, and performance of low-current operated TaOx-based devices as compared to other RRAM devices. This topical review will not only help for application of TaOx-based nanoscale RRAM devices but also encourage researcher to overcome the challenges in the future production.

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TaOx-based resistive switching memories: prospective and challenges

SRAM based configuration memory is the primary contributor to the large area, delay, and power consumption of FPGAs relative to ASICs. In [1] it is estimated that a 3D-FPGA with the configuration memory stacked on top of the FPGA logic and routing can achieve 57% smaller die area than a baseline 2D-FPGA in 65nm CMOS technology. Motivated by these potential performance gains, several programmable logic devices with different monolithically stacked configuration memory technologies have been reported [2–4]. These memory technologies, however, require materials and/or processes that may not be compatible or scalable with CMOS processes. This paper presents the first 3D-FPGA with stacked configuration memory based on the emerging nonvolatile Resistive RAM (RRAM) technology described in [5], which is both compatible and scalable with CMOS.

Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory

Series connection of metal-oxide semiconductor transistors and spin-injection-writable magneto-resistive junction devices based on logic-in-memory architecture realizes both programmable logic operation and nonvolatile storage function. A lookup table (LUT) circuit in field-programmable gate array fabricated by a 0.14µm magneto/semiconductor-hybrid process achieves area reduction by 2/3 compared to a conventional static random-access-memory-based one, and realizes complete standby power reduction.

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

This paper describes the design and fabrication of a digital look-up table (LUT) circuit using phase-change random access memory (PCRAM) cells. The LUT, fabricated in IBM 90 nm CMOS technology with embedded GST (Ge 2 Sb 2 Te 5 )-based phase-change memory (PCM) mushroom cell, performs programmable and non-volatile logic functions with a 1V supply. The PCRAM cell provides > 100X resistance transformation ratio and the LUT achieves a 453.4ps (average) propagation delay.

A non-volatile look-up table design using PCM (phase-change memory) cells

To overcome various concerns caused by scaling-down the device size, it is indispensable to introduce a new concept of heterogeneous 3D integration called a super-chip in which various kinds of device chips with different size, different devices and different materials are stacked. A key technology of self-assembly and electrostatic (SAE) temporary bonding has been developed to achieve a super-chip. Several kinds of super-chips are fabricated by stacking compound semiconductor device chip, photonic device chip and spintronic device chip on CMOS device chips.

Heterogeneous 3D integration — Technology enabler toward future super-chip

A novel reconfigurable logic block with SPRAM (spin-transfer torque RAM) is demonstrated. Magnetic elements of 50 times 200 nm2 in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kOmega (parallel) and the MR ratio is 91.7 %.

K. Miura

Papers

A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor