This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented. >

Berkeley reliability tools-BERT

In the study of semiconductor degradation, records of transconductance loss or threshold voltage shift over time are useful in constructing the cumulative distribution function (cdf) of the time until the degradation reaches a specified level. In this article, we propose a model with random regression coefficients and a standard-deviation function for analyzing linear degradation data. Both analytical and empirical motivations of the model are provided. We estimate the model parameters, the cdf, and its quantiles by the maximum likelihood (ML) method and construct confidence intervals from the bootstrap, from the asymptotic normal approximation, and from inverting likelihood ratio tests. Simulations are conducted to examine the properties of the ML estimates and the confidence intervals. Analysis of an engineering dataset illustrates the proposed procedures.

Statistical inference of a time-to-failure distribution derived from linear degradation

We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Furthermore, we show that the Static Noise Margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.

Impact of negative bias temperature instability on digital circuit reliability

Impact of Negative Bias Temperature Instability on )Digital Circuit

An approach for modeling hot-electron induced change in drain current that significantly improves the ease of parameter extraction and provides new capabilities for modeling the effect of bidirectional stressing and the asymmetrical I-V characteristics after stressing is presented. The change in the drain current, Delta I/sub D/ is implemented as an asymmetrical voltage-controlled current source and the new Delta I/sub D/ model is independent of the MOSFET model used for circuit simulation. The physical basis of the model, the analytical model equations, the implementation scheme in BERT (BErkeley Reliability Tools) simulator and simulation results for uni- and bidirectional circuit stressing are presented. >

A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the "zero crossing" effect caused by PMOSFET current enhancement. Saturation drain current, measured at V/sub gs/=V/sub ds/=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft/sub rise/ and 10/ft/sub fall/, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively. >

Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ft/sub rise/ and 10/ft/sub fall/ respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively. >

Hot-carrier-reliability design guidelines for CMOS logic circuits

Many analog MOSFET performance parameters are found to be very sensitive to hot-electron stress, especially compared with digital parameters that are normally monitored Drain output resistance degradation is characterized in detail using existing hot-electron reliability concepts and lifetime prediction models The impact of drain output resistance degradation on the performance of a CMOS single-ended output differential amplifier is found to be a sensitive function of the particular circuit design and operating conditions >

K.N. Quader

Papers

Berkeley reliability tools-BERT

A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation

Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation

Hot-carrier-reliability design guidelines for CMOS logic circuits

The effects of hot-electron degradation on analog MOSFET performance