Showing papers in "IEEE Transactions on Electron Devices in 1993"

Comparison of 6H-SiC, 3C-SiC, and Si for power devices

Abstract: The drift region properties of 6H- and 3C-SiC-based Schottky rectifiers and power MOSFETs that result in breakdown voltages from 50 to 5000 V are defined. Using these values, the output characteristics of the devices are calculated and compared with those of Si devices. It is found that due to very low drift region resistance, 5000-V SiC Schottky rectifiers and power MOSFETs can deliver on-state current density of 100 A/cm/sup 2/ at room temperature with a forward drop of only 3.85 and 2.95 V, respectively. Both devices are expected to have excellent switching characteristics and ruggedness due to the absence of minority-carrier injection. A thermal analysis shows that 5000-V, 6H-, and 3C-SiC MOSFETs and Schottky rectifiers would be approximately 20 and 18 times smaller than corresponding Si devices, and that operation at higher temperatures and at higher breakdown voltages than conventional Si devices is possible. Also, a significant reduction in the die size is expected. >

Mechanical-thermal noise in micromachined acoustic and vibration sensors

Abstract: The small moving parts in acoustic and vibration microsensors are especially susceptible to mechanical noise resulting from molecular agitation. For sensors designed for small-signal applications, this mechanical-thermal noise is often one of the limiting noise components. Several techniques for calculating the mechanical-thermal noise in acoustic and vibration sensors in general, and in micromachined sensors in particular, are reviewed. >

Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs

Abstract: A closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived. Expressions are also derived for the voltage slope and transition time of the RC interconnection and for coupling capacitance and crosstalk voltage height, which can be used in VLSI designs. Using the expressions, the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed. >

Scaling theory for double-gate SOI MOSFET's

Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Threshold voltage model for deep-submicrometer MOSFETs

Abstract: The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

On the bremsstrahlung origin of hot-carrier-induced photons in silicon devices

Abstract: Spectrally resolved absolute measurements of hot-carrier-induced photon emission in silicon are reported. In order to avoid uncertainties in geometrical and physical parameters, the simplest conceivable device, an avalanching p-n junction, was used. A photon emission efficiency of 2.9*10/sup 5/ photons with energy higher than 1.14 eV per carrier crossing the junction, independent of the lattice temperature down to 20 K, was measured. On the basis of these results the bremsstrahlung origin of the hot-carrier-induced light emission is critically reviewed. >

Correlation of stress-induced leakage current in thin oxides with trap generation inside the oxides

Abstract: Increases in pre-tunneling leakage currents in thin oxides after the oxides are subjected to high voltage stresses are correlated with the number of traps generated inside of the oxides by the high-voltage stresses. The densities of the traps are calculated using the tunneling front model and analyzing the transient currents that flowed through the oxide after removal of the stress voltage pulses. It is found that the trap distributions are relatively uniform throughout the small portion of the oxide sampled by the transient currents. The trap densities increase as the cube root of the fluence of electrons that passes through the oxide during the stress, independent of the stress polarity. The voltage dependence of the low-level pretunneling current is dependent on the sequence in which the stress voltage polarities and the low-level current measurement polarities are applied. The portion of the low-level pre-tunneling current that is not dependent on the polarity sequence is best fitted by a voltage dependence consistent with Schottky emission. >

Secondary emission formulas

Abstract: A minor revision is made to the author's 'A New Formula for Secondary Emission Yield' (ibid., vol.36, no.9, p.1963-7, September 1989) based on the work of A. Shih and C. Hor reported elsewhere in this issue (ibid. vol.40, no.4, p.824-9, Apr. 1993). >

Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation

Abstract: Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters. One of the most striking features of nu MOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified. >

Excimer-laser-annealed poly-Si thin-film transistors

Abstract: The crystallization of alpha -Si:H into poly-Si using an excimer laser has been examined. The resulting microstructure was found to be stratified into a large-grain surface region, formed from the liquid phase, and a fine-grain underlying layer, thought to be formed by solid phase crystallization. The threshold beam energies for these sequential phase changes were identified from surface reflectance measurements after crystallization and the energies increased with diminishing hydrogen content of the material. The electrical characteristics of thin-film transistors made with material crystallized at energies close to the melt threshold could be correlated with the limited depth of large-grain material. For significantly higher beam energies, coplanar structures showed a severe degradation in leakage current due to lateral diffusion of phosphorus, across the channel from the source and drain regions. When this effect was avoided, thin-film transistors with field-effect mobilities up to 160 cm/sup 2//V-s and on/off current ratios up to 10/sup 8/ were obtained. >

A new drain-current injection technique for the measurement of off-state breakdown voltage in FETs

Abstract: A simple three-terminal technique for measuring the off-state breakdown voltage of FETs is presented. With the source grounded, current is injected into the drain of the on-state device. The gate is then ramped down to shut the device off. In this process, the drain-source voltage rises to a peak and then drops. This peak represents an unambiguous definition of three-terminal breakdown voltage. In the same scan, a measurement of the two-terminal gate-drain breakdown voltage is also obtained. The method offers potential for use in a manufacturing environment, as it is fully automatable. It also enables easy measurement of breakdown voltage in unstable and fragile devices. >

Silicon carbide UV photodiodes

Abstract: SiC photodiodes were fabricated using 6 H single-crystal wafers. These devices have excellent UV responsivity characteristics and very low dark current even at elevated temperatures. The reproducibility is excellent and the characteristics agree with theoretical calculations for different device designs. The advantages of these diodes are that they will operate at high temperatures and are responsive between 200 and 400 nm and not responsive to longer wavelengths because of the wide 3-eV bandgap. The responsivity at 270 nm is between 70% and 85%. Dark-current levels have been measured as a function of temperature that are orders of magnitude below those previously reported. Thus, these diodes can be expected to have excellent performance characteristics for detection of low light level UV even at elevated temperatures. >

Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs

Abstract: An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the threshold-voltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed. The amount of drain-bias-induced depletion charge in the channel is estimated, and an expression for the distribution of this charge along the channel is developed. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized unified charge control model (UCCM) for short-channel MOSFETs are presented. The theory is applicable to deep-submicrometer devices with gate lengths larger than 0.1 mu m. The model is suitable for implementation in circuit simulators. >

Characterization of n-type beta -SiC as a piezoresistor

Abstract: SiC is currently being investigated for device applications involving high temperatures. The properties of n-type beta -SiC relevant to piezoresistive devices, namely the gauge factor (GF) and temperature coefficient of resistivity (TCR), are characterized for several doping levels. The maximum gauge factor observed was -31.8 for unintentionally doped (10/sup 16/-10/sup 17//cm/sup 3/) material. This gauge factor decreases with temperature to approximately half its room-temperature value at 450 degrees C. Unintentionally doped SiC has a roughly constant TCR of 0.72%/ degrees C over the range 25-800 degrees C and exhibits full impurity ionization at room temperature. Degenerately doped gauges (N/sub d/=10/sup 20//cm/sup 3/) exhibited a lower gauge factor (-12.7), with a more constant temperature behavior and a lower TCR (0.04%/ degrees C). The mechanisms of the piezoresistive effect and TCR in n-SiC are discussed, as well as their application towards sensors. >

Neuron MOS binary-logic integrated circuits. II. Simplifying techniques of circuit configuration and their practical applications

Abstract: For pt.I see ibid., vol.40, no.3, p.570-6 (March 1993). The fundamental circuit ideas developed by the authors in Part I are applied to practical circuits, and the impact of neuron MOSFET on the implementation of binary-logic circuits is examined. For this purpose, two techniques are presented to simplify the circuit configurations. It is shown that the input-stage D/A converter circuit in the basic configuration can be eliminated without any major problems, resulting in improved noise margins and speed performance. Then a design technique for symmetric functions, which is especially important when the number of input variables increases, is presented. The nu MOS logic design is characterized by a large reduction in the number of transistors as well as of interconnections. However, the decrease in transistor count comes at a cost in process tolerance due to the multivalued nature of the device operation. Test circuits were fabricated by a typical double-polysilicon CMOS process, and the measurement results are presented. >

Physical models for degradation effects in polysilicon thin-film transistors

Abstract: Experimental data showing the degradation in performance of polysilicon thin-film transistors (TFTs) under a variety of bias stress conditions are presented. A model is proposed to explain these effects whereby device performance degrades due to changes in the effective density of defect states in the material. Unlike single-crystal devices which degrade from hot-carrier effects, poly-Si TFTs are believed to degrade primarily due to the presence of high carrier densities in the channel. Good agreement between computer simulations of the device characteristics and experimental data ia demonstrated. It is shown that stressing under transient conditions leads to a more severe performance degradation than stressing under comparable steady-state conditions. >

On the profile design and optimization of epitaxial Si- and SiGe-base bipolar technology for 77 K applications. I. Transistor DC design considerations

Abstract: The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided. >

Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions

Abstract: The authors point out that time to breakdown (t/sub BD/) of silicon dioxide has a pronounced frequency dependence when it is measured under bipolar bias conditions. At high frequencies, bipolar t/sub BD/, can be enhanced by two orders of magnitude over the t/sub BD/, obtained using DC or unipolar pulse bias of the same frequency and electric field. The lifetime improvement is attributed to detrapping of holes. At high frequencies, the improvement is maximum because the trapped holes are concentrated at the interface where they can easily be removed upon field reversal. At low frequencies, there is less improvement because the trapped hole distribution extends further into the oxide. Two different mechanisms are proposed to explain the frequency-dependent spreading of the trapped hole distribution away from the interface. >

A novel and effective PECVD SiO/sub 2//SiN antireflection coating for Si solar cells

Abstract: It is shown that sequential plasma-enhanced chemical vapor deposition (PECVD) of SiN and SiO/sub 2/ can produce a very effective double-layer antireflection (AR) coating. This AR coating is compared with the frequently used and highly efficient MgF/sub 2//ZnS double layer coating. The SiO/sub 2//SiN coating improves the short-circuit current (J/sub SC/) by 47%, open-circuit voltage (V/sub OC/) by 3.7%, and efficiency (Eff) by 55% for silicon cells with oxide surface passivation. The counterpart MgF/sub 2//ZnS coating gives similar but slightly smaller improvement in V/sub OC/ and Eff. However, if silicon cells do not have the oxide passivation, the PECVD SiO/sub 2//SiN gives much greater improvement in the cell parameters, 57% in J/sub SC/, 8% in V/sub OC/, and 66% in efficiency, compared to the MgF/sub 2//ZnS coating which improves J/sub SC/ by 50%, V/sub OC/ by 2%, and cell efficiency by 54%. This significant additional improvement results from the PECVD deposition-induced surface/defect passivation. The internal quantum efficiency (IQE) measurements showed that the PECVD SiO/sub 2//SiN coating a absorbs fair amount of photons in the short-wavelength range ( >

A critical examination of the assumptions underlying macroscopic transport equations for silicon devices

Abstract: Assumptions used to derive macroscopic transport equations for silicon devices are critically examined. The position- and momentum-dependent distribution function for a silicon n-i-n diode is obtained from a rigorous solution to the Boltzmann equation, and various macroscopic quantities, such as the electron temperature tensor, energy and heat fluxes, and mobility, are rigorously evaluated and compared with widely used approximations. The common approximation of the heat flux by Fourier's law is shown to differ substantially from the actual heat flux. The results also show that at a given energy, the mobility within a submicrometer device can be much different than that for electrons at the same energy in bulk silicon. >

Lateral profiling of oxide charge and interface traps near MOSFET junctions

Abstract: A technique for measuring the lateral distributions of both interface traps and trapped oxide charge near the source/drain junctions in MOSFETs is presented in detail. This technique derives from the charge pumping method, is easy to implement, and allows ready separation of the interface-trap and oxide charge components. Some illustrative results are given. The various issues involved in its implementation and its practical limitations are discussed. >

High-mobility poly-Si thin-film transistors fabricated by a novel excimer laser crystallization method

Abstract: High-mobility poly-Si thin-film transistors (TFTs) were fabricated by a novel excimer laser crystallization method based on dual-beam irradiation. The new method can reduce the solidification velocity of the top Si layer by heating the bottom Si layer of the Si/SiO/sub 2//Si/glass substrate structure by means of laser irradiation not only from the front side but also from the back side. The grain size of poly-Si film was enlarged up to 2 mu m. The field-effect mobilities of the TFT exceeded 380 cm/sup 2//V-s for electrons and 100 cm/sup 2//V-s for holes. >

A new charge pumping method for determining the spatial distribution of hot-carrier-induced fixed charge in p-MOSFETs

Abstract: A charge pumping method is proposed for the direct measurement of the hot-carrier-induced fixed charge near the drain junction of p-MOSFETs. By holding the rising and falling slopes of the gate pulse constant and then varying the highest and lowest levels, the local threshold and local flatband voltages are readily obtained. The spatial distribution of fixed charges is directly calculated from the changes that occur in these curves after the application of stress. This method is quite simple and, specifically, requires no information about impurity concentrations in the substrate. The validity and reliability of the method have been supported by computer simulations. >

Simulating single-event burnout of n-channel power MOSFET's

Abstract: Single-event burnout of power MOSFETs is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFETs. >

Self-heating effects in basic semiconductor structures

Abstract: Investigates the effects of self-heating on the high current I-V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T/sub i/ to 3T/sub i/, where T/sub i/ is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T/sub i/ is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed. >

AC versus DC hot-carrier degradation in n-channel MOSFETs

Abstract: The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three damage mechanisms occurring during both DC and AC operation: interface states created at low and mid-gate voltages, oxide electron traps created under conditions of hole injection into the oxide, and oxide electron traps created under conditions of hot-electron injection. It is shown that the quasi-static contributions of these mechanisms fully account for hot-carrier degradation under AC stress. The AC stress model is applied to devices from several different technologies and to several different AC stress waveforms. Excellent agreement is obtained in each case. The results demonstrate the validity of the model for frequencies up to 1 MHz. The absence of any transient effect indicates that the model could be applicable at much higher frequencies. >

Bright organic electroluminescent devices with double-layer cathode

Abstract: Electroluminescent devices were fabricated using a diamine derivative and tris (8-quinolinolato) aluminum (III) complex as the hole transport layer and the emitting layer, respectively. The glass substrate/anode/hole transport layer/emitting layer/cathode cells structure was employed. The anode was indium-tin-oxide (ITO) transparent electrode, and the cathode was a double layer consisting of first layer of Mg or Li and the second layer of Ag. Intense bright green emission with luminance of 40400 cd/m/sup 2/ was achieved at 18-V with a current density of 330 mA/cm/sup 2/ for the cell with the Al complex doped with 1 mol.% of coumarin 6 and Li/Ag as the cathode. >

Analysis of the effects of scaling on interconnect delay in ULSI circuits

Abstract: A model has been developed to assess interconnect delay in ULSI circuits as dimensions are scaled deep into the submicrometer regime. In addition to RC delay, the model includes the effects of current density limitations imposed to prevent electromigration of the interconnect metallurgy. The authors confirm that interconnect delays will contribute significantly to the total circuit delay in future ULSI circuits unless improvements are implemented. However, contrary to previous reports, the authors show that lowering the resistivity of the interconnect will not result in significant improvements in interconnect switching speed. Only by introducing lower dielectric constant interlevel insulators or by improving the electromigration resistance of the interconnect can significant performance enhancements be realized. >

Time dependence of p-MOSFET hot-carrier degradation measured and interpreted consistently over ten orders of magnitude

Abstract: Hot-carrier degradation is measured and analyzed over ten orders of magnitude in time for three buried-channel p-MOSFET types with different oxide thicknesses. The effects of oxide charge and interface states are separated by using the charge-pumping technique. Two dominating effects are sufficient to account for the degradation. For worst case degradation, negative oxide charge and interface states are generated by electrons near the drain. This charge is distributed homogeneously over the oxide thickness and it attracts an inversion layer that extends the drain and reduces the effective transistor length logarithmically in time. Simultaneously, this inversion layer prevents substantial degradation related to the interface states, since it masks their effects. A simple model for the logarithmic time dependence is presented. At more negative gate voltages, holes cause interface states that reduce the transconductance with a power-law time dependence, comparable to the worst case n-MOSFET degradation. >

Secondary emission properties as a function of the electron incidence angle

Abstract: Computer codes being developed to improve the understanding of crossed-field amplifier (CFA) performance require a more complete and reliable database of the secondary electron emission properties of the electrode materials than exists in the literature. The authors describe an experimental method and present results of secondary emission yield measurements on molybdenum surfaces, both clean and gas-exposed. The surface cleanliness was monitored by Auger electron spectroscopy (AES), and all measurements were made under ultrahigh-vacuum conditions (better than 1*10/sup -10/ torr). The results differ from the existing data for which the surface cleanliness was not determined. The secondary electron emission yields were measured as a function of the primary electron energy and also of the angle of incidence. The results were fitted with the analytical expressions of J.R.M. Vaughan (1989), with good overall agreement if Vaughan's formulas are slightly modified. >