Nanotopography-guided tissue engineering and regenerative medicine ☆

Packaging is a core technology to leverage the functions and the performances of micro- and nano-structures in a system. In order to bring them to application, the gap between component and environment has to be bridged by providing reliable interfaces. This paper reviews the packaging of optoelectronic, photonic, and microelectromechanical systems (MEMS) components. State-of-the-art requirements, standard technologies, and approaches are considered. Recent trends and research results in the packaging of advanced photonic, MEMS, Si-photonic components, and in 3-D, heterogeneous integration, and SiP are discussed.

Review of Packaging of Optoelectronic, Photonic, and MEMS Components

The exploration of vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning, and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. For the first time, Fermilab has organized a 3D MPW run, to which more than 25 different designs have been submitted by the consortium.

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Vertically Integrated Circuits at Fermilab

The balance between extinction ratio (ER) and insertion loss (IL) dictates strict trade-off when designing travelling-wave electro-optic modulators. This in turn entails significant compromise in device footprint (L3dB) or energy consumption (E). In this work, we report a nanoscale modulator architecture that alleviates this trade-off while providing dynamic reconfigurability that was previously unattainable. This is achieved with the aide of three mechanisms: (1) Utilization of epsilon-near-zero (ENZ) effect, which maximizes the attainable attenuation that an ultra-thin active material can inflict on an optical mode. (2) Non-resonant coupled-plasmonic structure which supports modes with athermal long-range propagation. (3) Triode-like biasing scheme for flexible manipulation of field symmetry and subsequently waveguide attributes. By electrically inducing indium tin oxide (ITO) to be in a local ENZ state, we show that a Si/ITO/HfO2/Al/HfO2/ITO/Si coupled-plasmonic waveguide can provide amplitude modulation with ER = 4.83 dB/μm, IL = 0.03 dB/μm, L3dB = 622 nm and E = 14.8 fJ, showing at least an order of magnitude improvement in modulator figure-of-merit and power efficiency compared to other waveguide platforms. Employing different biasing permutations, the same waveguide can then be reconfigured for phase and 4-quadrature-amplitude modulation, with actively device length of only 5.53 μm and 17.78  μm respectively.

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Dynamically reconfigurable nanoscale modulators utilizing coupled hybrid plasmonics

The ISIS is an ultra-fast image sensor with in-pixel storage. The evolution of the ISIS in the past and in the near future is reviewed and forecasted. To cover the storage area with a light shield, the conventional frontside illuminated ISIS has a limited fill factor. To achieve higher sensitivity, a BSI ISIS was developed. To avoid direct intrusion of light and migration of signal electrons to the storage area on the frontside, a cross-sectional sensor structure with thick pnpn layers was developed, and named “Tetratified structure”. By folding and looping in-pixel storage CCDs, an image signal accumulation sensor, ISAS, is proposed. The ISAS has a new function, the in-pixel signal accumulation, in addition to the ultra-high-speed imaging. To achieve much higher frame rate, a multi-collection-gate (MCG) BSI image sensor architecture is proposed. The photoreceptive area forms a honeycomb-like shape. Performance of a hexagonal CCD-type MCG BSI sensor is examined by simulations. The highest frame rate is theoretically more than 1Gfps. For the near future, a stacked hybrid CCD/CMOS MCG image sensor seems most promising. The associated problems are discussed. A fine TSV process is the key technology to realize the structure.

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Toward One Giga Frames per Second — Evolution of in Situ Storage Image Sensors

We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

Cu Retardation Performance of Extrinsic Gettering Layers in Thinned Wafers Evaluated by Transient Capacitance Measurement

To recover visual sensation of blind patients, we have proposed a novel three dimensionally (3D) stacked retinal prosthesis chip in which several LSI chips such as consisting of photodetector, signal processing circuit and stimulus current generator are vertically stacked and electrically connected using 3D integration technology. In this work, we developed several key process for realizing 3D stacked retinal prosthesis chip. Fine sized Cu TSV of 10 µm width and 30 µm depth was successfully formed from the back side of the thinned prosthesis chip. The prosthesis chip with the back side Cu TSVs was flip-chip bonded to Si substrate/flexible substrate through Cu/Sn micro-bumps for evaluating the feasibility of 3D integration technology.

3D integration technology for 3D stacked retinal chip

In this paper, we describe the fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS). To realize high speed image capturing sensor, we have proposed a block-parallel signal processing with three-dimensional (3D) structure. Using 3D structure, the different function layers are stacked vertically and interconnected electrically by through-Si vias (TSVs), which can improve sensor performance and signal band width. On the other hand, the fixed pattern noise (FPN), caused by the circuit device variation, becomes a critical challenge. Experiments on the fabricated pixel circuit have been implemented in a single-layer (two-dimensional) 0.18-µm CMOS image sensor technology. With the analog CDS, the FPN of pixel circuit is reduced by 8.6%. To eliminate the FPN of parallel ADC, a digital CDS technique is implemented. The proposed ADC with digital CDS is designed in a two-dimensional 0.18-µm CMOS technology. The ADC design, including an 8-bit memory, a 6-bit memory, a subtraction circuit, and a comparator, occupies 100×100µm2 area and 0.9mW with supply voltage 1.8 V and 1 MS/s conversion rate. The functional simulation and measurement results confirm that our techniques can effectively reduce fixed pattern noise.

A parallel ADC for high-speed CMOS image processing system with 3D structure

We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

K-W Lee

Papers

3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

Cu Retardation Performance of Extrinsic Gettering Layers in Thinned Wafers Evaluated by Transient Capacitance Measurement

3D integration technology for 3D stacked retinal chip

A parallel ADC for high-speed CMOS image processing system with 3D structure

Characterization of chip-level hetero-integration technology for high-speed, highly parallel 3D-stacked image processing system