Mechanical failure modes of chronically implanted planar silicon-based neural probes for laminar recording

Wafer-level heterogeneous integration technologies for microoptoelectromechanical systems (MOEMS), microelectromechanical systems (MEMS), and nanoelectromechanical systems (NEMS) enable the combination of dissimilar classes of materials and components into single systems. Thus, high-performance materials and subsystems can be combined in ways that would otherwise not be possible, and thereby forming complex and highly integrated micro- or nanosystems. Examples include the integration of high-performance optical, electrical or mechanical materials such as monocrystalline silicon, graphene or III-V materials with integrated electronic circuits. In this paper the state-of-the-art of wafer-level heterogeneous integration technologies suitable for MOEMS, MEMS, and NEMS devices are reviewed. Various heterogeneous MOEMS, MEMS, and NEMS devices that have been described in literature are presented.

Wafer-Level Heterogeneous Integration for MOEMS, MEMS, and NEMS

Packaging is a core technology to leverage the functions and the performances of micro- and nano-structures in a system. In order to bring them to application, the gap between component and environment has to be bridged by providing reliable interfaces. This paper reviews the packaging of optoelectronic, photonic, and microelectromechanical systems (MEMS) components. State-of-the-art requirements, standard technologies, and approaches are considered. Recent trends and research results in the packaging of advanced photonic, MEMS, Si-photonic components, and in 3-D, heterogeneous integration, and SiP are discussed.

Review of Packaging of Optoelectronic, Photonic, and MEMS Components

We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an important manufacturing technique for advanced microelectronics and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics. Commercially available alignment tools provide prebonding wafer-to-wafer misalignment tolerances on the order of 0.25 μm. However, better alignment accuracy is required for increasing demands for higher density of through-strata vias and bonded interstrata vias, whereas issues with wafer-level alignment uniformity and reliability still remain. Three-dimensional processes also affect the alignment accuracy, although the misalignment could be reduced to certain extent by process control. This paper provides a comprehensive review of current research activities over wafer-to-wafer alignment, including alignment methods, accuracy requirements, and possible misalignments and fundamental issues. Current misalignment concerns of the major bonding approaches are discussed with detailed alignment results. The fundamental issues associated with wafer alignment are addressed, such as alignment mechanisms, uniformity, reproducibility, thermal mismatch, and materials. Alternative alignment approaches are discussed, and perspectives for wafer-to-wafer alignment are given.

https://ir.nctu.edu.tw:443/bitstream/11536/20926/1/000293751100015.pdf

Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review

We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

New heterogeneous multi-chip module integration technology using self-assembly method

We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D) and hetero integration of complementary metal-oxide semiconductors (CMOS) and microelectromechanical systems (MEMS). By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF) aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

https://www.mdpi.com/2072-666X/2/1/49/pdf

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

A retinal prosthesis system with a three-dimensionally (3D) stacked LSI chip has been proposed. We fabricated a new implantable stimulus electrode array deposited with Platinum-black (Pt-b) on a polyimide-based flexible printed circuit (FPC) for the electrical stimulation of the retinal cells. Impedance measurement of the Pt-b electrode–electrolyte interface in a saline solution was performed and the Pt-b electrode realized a very low impedance. The power consumption at the electrode array when retinal cells were stimulated by a stimulus current was evaluated. The power consumption of the Pt-b stimulus electrode array was 91% lower than that of a previously fabricated Al stimulus electrode array due to a convexo-concave surface. In the cytotoxicity test (CT), we confirmed that Pt implantation induced no cellular degeneration of the rat retina. In the animal experiments, electrically evoked potential (EEP) was successfully recorded using Japanese white rabbits. These results indicate that electrical stimulation using the Pt-b stimulus electrode array can restore visual sensation.

Evaluation of Platinum-Black Stimulus Electrode Array for Electrical Stimulation of Retinal Cells in Retinal Prosthesis System

We have proposed a new implantable neural recording system, which we call the brain signal processing system (BSPS). In this system, LSI chips such as amplifiers, analog-to-digital converters, and multiplexers are integrated on the Si microelectrode array. To analyze the brain functions or to develop medical treatments for brain disorders, a high-density recording of action potentials is strongly required. To realize high-density recording of action potentials, we propose a novel Si double-sided microelectrode that has recording sites on both front and back sides. The back-side recording sites are connected to a recording apparatus by wire bonding through Si via holes. We fabricated the carefully designed Si double-sided microelectrode and evaluated the electrical characteristics of the Si microelectrode. The front- and back-side recording sites had impedance values of 2.5 and 2.7 MΩ at 1 kHz, respectively, which indicated that both recording sites have equivalent characteristics. An in vitro experiment of neuronal action potential recording using the fabricated Si double-sided microelectrode was performed. The CA1 areas of 400-µm-thick hippocampal slices obtained from the brains of guinea pigs were employed, and we successfully recorded neuronal action potentials from the recording sites of both sides.

Risato Kobayashi

Papers

New heterogeneous multi-chip module integration technology using self-assembly method

3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

Evaluation of Platinum-Black Stimulus Electrode Array for Electrical Stimulation of Retinal Cells in Retinal Prosthesis System

Development of Si Double-Sided Microelectrode for Platform of Brain Signal Processing System