A semiempirical model for carrier mobility in silicon inversion layers is presented. The model, strongly oriented to CAD (computer-aided design) applications, is suitable for two-dimensional numerical simulations of nonplanar devices. A local mobility function, set up in terms of a simple Mattiessen's rule, provides a careful description of MOSFET operation in a wide range of normal (or gate) electric fields, channel impurity concentrations of between 5*10/sup 14/ cm/sup -3/ and 10/sup 17/ cm/sup -3/ for the acceptor density of states and 6*10/sup 14/ cm/sup -3/ and 3*10/sup 17/ cm/sup -3/ for the donor density of states; and temperatures between 200 K and 460 K. Best-fit model parameters are extracted by comparing the calculated drain conductance with a very large set of experimental data points. >

A physically based mobility model for numerical simulation of nonplanar devices

A MESFET model is presented that is suitable for use in conventional, time-domain circuit simulation programs. The parameters of the model are evaluated either from experimental data or from more detailed device analysis. The model is shown to be more complete than earlier models, which neglect transit-time and other effects. An integrated circuit (IC) design example is discussed.

A MESFET Model for Use in the Design of GaAs Integrated Circuits

The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Lucky-electron model of channel hot-electron injection in MOSFET'S

A study of the turn-on of very thin dielectric MOS devices from subthreshold to strong inversion is described. A functional form has been found for the derivative of channel charge with respect to gate voltage, the derivative of channel charge with respect to distance along the channel, and the electric field along the channel in this transition region. A method to extract electron mobility versus gate voltage independent of any arbitrarily defined threshold voltage has been shown. Measured data on the electron mobility vs gate voltage for 100A gate dielectric MOS devices are reported.

Charge accumulation and mobility in thin dielectric MOS transistors

The LDD structure, where narrow, self-aligned n-regions are introduced between the channel and the n+source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of the n-dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n-regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 µm. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 × basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.

Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor

An accurate numerical model of avalanche breakdown in MOSFET's is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFET's and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFET's. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFET's. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFET's over n-MOSFET's from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.

A numerical model of avalanche breakdown in MOSFET's

A field-dependent mobility model for use in two-dimensional numerical analysis of MOSFET's is proposed. This model takes into account two field components: One is the gate field which induces carriers in the inversion layer and the other is the drain field which transports carriers to the drain. Mobility is assumed to be a product of two functions, each of which includes only a field component perpendicular or parallel to the current flow ( E_{\perp} or E_{\parallel} ), that is \micro = \micro_{0} f (N_{B}, E_{\parallel})g(E_{\perp}), with \micro_{0} and N B being a constant and the impurity concentration, respectively. This equation is applied to calculate the mobility at each mesh point in the numerical analysis. The validity of the present model is demonstrated using several MOSFET structures, for example, conventional structures with short and long gate lengths, and offset-gate structrues with channel-doped layers. Reasonable agreement is found between calculated and experimental results under moderate bias conditions. Flat-band voltage, V FB , is assumed to be the only fitting parameter and is adjusted once for each set of samples. Quantitative agreement for short-channel MOSFET's is improved, typically by a factor of 2, and errors are within 20 percent with respect to the experiments.

Field-dependent mobility model for two-dimensional numerical analysis of MOSFET's

A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 106cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.

A mobility model for carriers in the MOS inversion layer

Stability criteria of GaAs junction-gate FET's are studied by two-dimensional numerical analysis. The analysis covers the wide range of device geometry from the state of the art FET to the so-called Gunn effect digital devices. It is found that a GaAs FET exhibits either of the following three types of characteristics depending upon device geometry and doping concentration. First, for a thin channel with high doping concentration, the device tends to behave as a normal junction-gate FET with saturating current-voltage characteristics. This is even true when the n-l (device length) and n.d (device thickness) products exceed the previously accepted criteria for Gunn oscillation. Second, a stable negative resistance (SNR) is observed in devices with a moderate channel thickness. Third, for a thick channel, the device exhibits a Gunn oscillation with the domain propagating from the gate edge to the drain. These three categories of behavior are mapped on the nd plane with the help of simple analytic considerations. The map is found to compare well with experimental results.

Two-dimensional numerical analysis of stability criteria of GaAs FET's

Design criteria of triode-like JFET's are studied by fully utilizing two-dimensional numerical analysis. The current is caused by tlie carriers injected over a potential barrier in a depleted channel. In contrast to normal pentode-like FET'S, the drain field plays an important role reducing the barrier height and thus causing triode-like I-V characteristics. Triode-like characteristics depend strongly on device geometry. This operation can be realized only in short gate devices. The channel thickness a is an essential parameter in determining the operational mode. The devices operate as triodes or pentodes corresponding to thin or thick channels, respectively. If applied to low-resistance load direct-drive circuits, the mixed characteristics situated between the triode- and pentode-like ones, are more desirable when compared to pure triode-like ones, This is because of their low on-resistance and high ac power efficiency. The gate-drain distance l gd is also essential in determining breakdown voltage. The design criteria are discussed and an optimum design specified on the N D (channel doping)- a and N_{D} - l_{gd} planes with respect to triode-like characteristics, circuit application and breakdown phenomena. Calculated results are compared with experiments and good agreement is found without using any adjustable parameters. The present design criteria will be useful for designing triode-like JFET's.

K. Yamaguchi

Papers

A numerical model of avalanche breakdown in MOSFET's

Field-dependent mobility model for two-dimensional numerical analysis of MOSFET's

A mobility model for carriers in the MOS inversion layer

Two-dimensional numerical analysis of stability criteria of GaAs FET's

Optimum design of triode-like JFET's by two-dimensional computer simulation