In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 µm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 µA from a single 1.8 V supply voltage.

A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter

Two 4-bit active phase shifters integrated with all digital control circuitry in 0.13-mu m RF CMOS technology are developed for X- and Ku-band (8-18 GHz) and K-band (18-26 GHz) phased arrays, respectively. The active digital phase shifters synthesize the required phase using a phase interpolation process by adding quadrature-phased input signals. The designs are based on a resonance-based quadrature all-pass filter for quadrature signaling with minimum loss and wide operation bandwidth. Both phase shifters can change phases with less than about 2 dB of RMS amplitude imbalance for all phase states through an associated DAC control. For the X- and Ku-band phase shifter, the RMS phase error is less than 10 degrees over the entire 5-18 GHz range. The average insertion loss ranges from -3 dB; to -0.2 dB at 5-20 GHz. The input P-1dB for all 4-bit phase states is typically - 5.4 +/- 1.3 dBm at 12 GHz in the X- and.Ku-band phase shifter. The K-band phase shifter exhibits 6.5-13 degrees of RMS phase error at 15-26 GHz. The average insertion loss is from -4.6 to -3 dB at 15-26 GHz. The input P-1dB of the K-band phase shifter is -0.8 +/- 1.1 dBm at 24 GHz. For both phase shifters, the core size excluding all the pads and the output 50 Omega matching circuits, inserted for measurement purpose only, is very small, 0.33 x 0.43 mm(2). The total current consumption is 5.8 mA in the X- and Ku-band phase shifter and 7.8 mA in the K-band phase shifter, from a 1.5 V supply voltage.

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0.13-mu m CMOS phase shifters for X-, Ku-, and K-band phased arrays - eScholarship

This paper presents an all-passive, 4-element, phased-array beamformer based on a differential, reflection-type phase shifter (RTPS) operating in the 60GHz band. The RTPS consists of a differential, vertically-coupled, coupled-line hybrid and variable, parallel-LC, resonant, reflective loads, both of which enable low-loss millimeter-wave operation. The design considerations for a silicon-based implementation of all the beamformer elements are discussed in detail. In particular, the influence of the different RTPS components on its insertion loss is analyzed. The beamformer IC and a breakout of the RTPS are implemented using CMOS-only features of IBM's 8HP 0.13ijm SiGe BiCMOS process, and employ areas of 2.1mm2 and 0.33mm2, respectively, without probe pads. Differential s-parameter measurements at 60GHz show a phase-shift range greater than 150°, insertion losses of 4–6.2dB in the RTPS and 14–16dB in the beamformer, and an isolation better than 35dB between adjacent beamformer channels. Measurements across temperature and process variations are also presented.

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A silicon-based, all-passive, 60 GHz, 4-element, phased-array beamformer featuring a differential, reflection-type phase shifter

This brief presents a novel biquadratic cell (biquad) based on the flipped-source-follower (FSF) circuit. The main idea is to exploit the FSF circuit as a basic building block for a low-pass second-order filter, taking advantage of its well-known strengths, like low-output impedance, low-noise, large in-band linearity, and low power. Thanks to the very essential FSF circuit, the resulting biquad is a power-efficient broad bandwidth stage, with very low-noise performance. In order to validate the biquad design idea, extensive circuital simulation results will be presented. The filter design example synthesizes a third-order low-pass transfer function and consumes 2.3 mW from a single 1.8 $\text{V} {@} {V} _{\text{DD}} $ . Input noise spectral density is 7 nV/vHz. Linearity has been evaluated in terms of IIP3 (25 dBm) and THD (−40 dBc at 380 ${\text{mV}}_{\text {0-PEAK}} $ output voltage swing, resulting in 62-dB SNR). Hence, a very promising figure-of-merit (i.e., 165 $\text{J}^{{-1}}$ ) has been achieved.

A Biquadratic Cell Based on the Flipped-Source-Follower Circuit

As of today, the highest cut-off frequency low-pass continuous-time analog filters are in the frequency band of 1 to 3GHz [2,4–6], targeting applications like UWB communications or hard disk drives. Nevertheless, bands much higher, of about 10GHz, are to be addressed in the near future. This paper demonstrates an active low-pass filter tunable from 1 to 10GHz in 65nm CMOS, which is to our knowledge the highest ever cutoff frequency reported.

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A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications

For the analog baseband section of a 60GHz receiver for fast download applications, two 5th order Butterworth filters with cutoff frequency of 880MHz and 1.76GHz for 60GHz radios are implemented in 40nm low power digital CMOS, using Sallen and Key biquads. Drawing 25/21mA from a 1.1V supply, an IIP3 of −13/−12dBV to −16.7/−18.3dBV and an input-referred noise of 320/280µVrms are measured for the 880/1760MHz filter.

A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS

To enable mass-market applications based on short- range wireless communication around 60 GHz at datarates above 1 Gbps, cheap implementation technologies are needed. The radios for these applications often use antenna arrays with beamforming to improve the link budget. This work discusses the state-of-the-art on CMOS beamforming architectures and describes the different parts of a wireless link that is built around a four-antenna array on a PCB that also contains 45nm digital CMOS receiver ICs with beamforming capabilities. Keywords-CMOS, 60 GHz, mm-wave, phased arrays.

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Low-Cost CMOS-Based Receive Modules for 60 GHz Wireless Communication

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.

Karen Scheir

Papers

A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS

Low-Cost CMOS-Based Receive Modules for 60 GHz Wireless Communication

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies