Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.

Power distribution system design methodology and capacitor selection for modern CMOS technology

Hardware-based secure integrated circuit (IC) chips with implemented cryptographic algorithms are vulnerable to practical attacks analyzing side-channel (SC) leakage such as electromagnetic radiation. Correlation power analysis (CPA) is a real threat to secret key crypto ICs. Therefore, the information leakage risks need to be evaluated at the design stage of secure devices. This letter proposes a fast power leakage simulation method for hardware-implemented cryptographic ICs. The power delivery network (PDN) of cryptographic hardware including a silicon substrate is modeled by a chip power model (CPM) and a chip package system (CPS) board model. The proposed method was applied to the advanced encryption standard (AES) test chip implemented by the flip-chip ball grid array (FC-BGA) assembly technology. The simulation results are evaluated by CPA for the SC leakage during plaintext encryption propagating through PDN and silicon substrate. The measurement and simulation successfully find 128-bit secret key on CPA attack. The proposed simulation technique reduces the time required in the exploration of SC leakage risks for secure device designs.

A Fast Side-Channel Leakage Simulation Technique Based on IC Chip Power Modeling

To reduce the noise created by a power delivery network, the number, the value of decoupling capacitors and their arrangement on the board are critical to reaching this goal. This work deals with specific improvements, implemented on a genetic algorithm, which used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values. Measurements are performed on a specifically manufactured board in order to validate the effectiveness of the proposed algorithm and the optimization results obtained for a specific example board.

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Efficient Iterative Process Based on an Improved Genetic Algorithm for Decoupling Capacitor Placement at Board Level

A well-designed power delivery network (PDN) demands a set of efficient and effective modeling and optimization methodology for the Chip-Package-PCB System. This paper work provided and validated the hybrid target impedance for the PDN impedance optimization in frequency domain and the physics-based equivalent circuit model with small signal model for voltage response validation in time domain. The hybrid target impedance defined with current profile-based discrete and continuous target impedance. Two key impedance points in discrete were identified for on-chip worst case switching scenario and voltage regulator module switching ripple, more points can be added if specific core power switching scenario identified. The continuous impedance points are from the conventional target impedance by voltage ripple to dynamic current change. This hybrid method provides a more effective and convergent way to perform system level decoupling capacitors optimization in frequency domain and to meet voltage specification in time domain, also to avoid overdesigning for cost saving.

Power Delivery Network Optimization Approach using an Innovative Hybrid Target Impedance

Far-end crosstalk (FEXT) noise is a critical factor that affects signal integrity performance in high-speed systems. The FEXT level is sensitive to the dielectric inhomogeneity of the stripline in fabricated printed circuit boards (PCB). Stripline is typically modeled as a 2-layer model with core and prepreg layers. However, in reality, the stripline is laminated by multiple inhomogeneous dielectric layers (IDL). The dielectric layers of the stripline are laminated with epoxy resin and glass bundles. The dielectric permittivity (e r ) of the epoxy resin and glass bundles are different, which causes the inhomogeneity of the dielectric layers while also increasing the FEXT magnitude. Therefore, a typical 2-layer structure is inaccurate to model the FEXT. In this paper, the stripline model is constructed with the core, prepreg, and resin pocket layers. To analyze the stripline with three IDL, a practical superposition method is proposed. A design guideline to mitigate the FEXT level in the stripline design is proposed based on the method.

Far-End Crosstalk Analysis for Stripline with Inhomogeneous Dielectric Layers (IDL)

The goal of a well-designed power delivery network (PDN) is to deliver desired voltage level from the source to destination, in other words, to minimize voltage noise and errors delivered to chip. This paper provides power integrity engineers a guideline to model PDN agilely in a simplified method and choose specific voltage regulator module model under specific circumstances. These comparisons and studies present the advantage of this novel methodology using equivalent circuit model for system level power integrity transient analysis.

A Novel System-Level Power Integrity Transient Analysis Methodology using Simplified CPM Model, Physics-based Equivalent Circuit PDN Model and Small Signal VRM Model

Skew is unintentionally introduced within a differential pair, through misalignment of conductors and glass fiber bundles in Printed Circuit Board (PCB) dielectric layers. Manufacturers do not control interposition of specific glass bundles to supplied board design (artwork). Therefore, an unknown and random factor is added to each produced PCB. Current paper describes a method that utilizes a set of measurements and numerical models to estimate worst-case skew for the aforementioned effect. First, test vehicles are built, and then cross-sections are analyzed with Scanning Electron Microscope (SEM) for precise measurements. Numerical models are constructed to correlate with real DUT; after correlation is achieved, relative location of conductors to glass bundles is swept to obtain best and worst case skew.

Measurement and correlation-based methodology for estimating worst-case skew due to glass weave effect

In this paper, effect of time delay skew (TDS) on differential insertion loss (IL) is studied in both weak and strong forward coupling cases. It is showed that TDS impacts differential IL and impact depends on amount of forward coupling. To predict additional differential IL due to TDS, analytical formula is derived and heuristic formula is constructed based on fitting to simulation results in weak and strong forward coupling cases, respectively. The predictions are validated by simulations and measurements.

Effect of time delay skew on differential insertion loss in weak and strong coupled PCB traces

It is understood very well that at 20Gbps and beyond, P/N skew from fiber weave effect in printed circuit board (PCB) has to be taken into account. Several studies have been done to measure and quantify the effect of glass weave but very few have offered techniques to budget for P/N skew. System companies need an effective way to capture glass weave skew and budget for it in channel designs. Using transmission line theory, we analytically calculate differential loss due to P/N skew, study the effect of P/N skew on eye performance for SerDes IP and explore dependency of P/N skew on PCB materials. This paper studies effect on S-parameters, SerDes eye performance due to skew that can help SI engineer to effectively budget for P/N skew as part of channel link budget.

Kartheek Nalla

Papers

A Novel System-Level Power Integrity Transient Analysis Methodology using Simplified CPM Model, Physics-based Equivalent Circuit PDN Model and Small Signal VRM Model

Power Delivery Network Optimization Approach using an Innovative Hybrid Target Impedance

Measurement and correlation-based methodology for estimating worst-case skew due to glass weave effect

Effect of time delay skew on differential insertion loss in weak and strong coupled PCB traces

Effective channel budget technique for high-speed channels due to differential P/N skew