We introduce a rapid interferer detector that uses compressed sampling (CS) with a quadrature analog-to-information converter (QAIC). By exploiting bandpass CS, a blind sub-Nyquist sampling approach, the QAIC offers an energy efficient and rapid interferer detection over a wide instantaneous bandwidth. The QAIC front end is implemented in 65 nm CMOS in 0.43 mm 2 and consumes 81 mW from a 1.1 V supply. It senses a frequency span of 1 GHz ranging from 2.7 to 3.7 GHz (PCAST Band) with a resolution bandwidth of 20 MHz in 4.4 µs, 50 times faster than traditional sweeping spectrum scanners. Rapid interferer detector with the bandpass QAIC is two orders of magnitude more energy efficient than traditional Nyquist-rate architectures and one order of magnitude more energy efficient than existing low-pass CS methods. Thanks to CS, the aggregate sampling rate of the QAIC interferer detector is compressed by 6.3 $\times$ compared to traditional Nyquist-rate architectures for the same instantaneous bandwidth.

Wideband Rapid Interferer Detector Exploiting Compressed Sampling With a Quadrature Analog-to-Information Converter

Sub-sampling phase detectors (SSPDs) have recently been demonstrated to enable phase-locked loop (PLL) realizations with very low in-band noise. However, the PLL becomes susceptible to disturbances or interference via substrate or power supply coupling as experienced in systems on chip (SOCs), which could put the PLL out of lock. A tri-state phase-frequency detector with a dead-zone is traditionally added to act as an auxiliary frequency-locked loop (FLL) to enable the PLL to regain lock, albeit after a long delay. We propose a different solution to combine a tri-state PFD with an SSPD wherein the PLL is prevented from losing its lock while simultaneously achieving an improved in-band phase noise performance. A 2.2 GHz integer-N PLL has been prototyped in a 65 nm CMOS process to demonstrate the advantages of the proposed combined phase detector. It was experimentally verified that the PLL is more robust to disturbances than a PLL with a sub-sampling phase detector; it achieves a measured in-band phase noise of $-$ 122 dBc/Hz when operating with the proposed combined PD from a 1.1 V supply voltage.

A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-locked clock multipliers have demonstrated some of the lowest jitters for a given power consumption (jitter-power ${\text {FoM}}_{j}$ metric). However, they contain a tradeoff between the spur and noise performance, where techniques incorporated for spur reduction adversely affect jitter or power performance. A new dividerless Type-I sampling PLL, called the reference sampling PLL (RS-PLL), which estimates the voltage-controlled oscillator (VCO) phase error by sampling the reference sine wave with a VCO square wave is demonstrated. A clock-and-isolation buffer which accelerates the VCO sine wave to a square wave sampling clock and simultaneously isolates the VCO tank from spur mechanisms in the sampler is included in place of a traditional reference buffer. By combining sampling clock buffer and VCO isolation functionalities into a single block, the RS-PLL eliminates the noise penalty of two separate buffers. The power penalty due to sampling at VCO frequency is restricted by limiting the activity of the switching circuits to the region around the reference zero crossing where the phase error information exists. The prototype RS-PLL implemented in 65-nm CMOS achieves a jitter-power ${\text {FoM}}_{j}$ of <−251 dB between 2.05 and 2.55 GHz with a reference spur of <−66 dBc at 50 MHz. In doing so, it improves upon the simultaneous noise and spur performance achieved by current state-of-the-art clock multipliers.

A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

A 16-modulo fractional-N sub-sampling phase-locked loop (SSPLL) with a quadrature voltage-controlled oscillator (VCO) interpolating 16 output phases is presented in this paper. Automatic soft switching between the sub-sampling phase control loop and the frequency control loop is proposed to improve loop robustness against perturbations and interferences, achieving more stable loop dynamics for a larger range of phase errors compared with prior art SSPLL designs. A capacitive phase interpolation network is implemented for 16-phase clock generation starting from quadrature phases. The 16 phases are further utilized to achieve fractional-N operation with a sub-sampling phase detector. This passive phase interpolation at the VCO frequency introduces no extra noise or power and avoids in-band phase noise degradation for fractional-N mode. Implemented in a 130-nm CMOS technology, the SSPLL chip achieves a measured in-band phase noise of −120 dBc/Hz and a measured integrated jitter of 158 fs at 2.4 GHz, while consuming 21 mW with 16 output phases. The measured reference spur and fractional spur levels are −72 and −52 dBc, respectively.

A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching

The modulated wideband converter receiver architecture leverages compressive sensing techniques to improve flexibility for cognitive radio applications. We present a prototype integrated circuit that adds signal reception to previously demonstrated signal detection. By refactoring the mixing sequence between signal detection and reception, we enable targeted reception and blocker rejection. We algorithmically design a three-level mixing sequence and additionally employ delay-based harmonic cancellation. When applied together in our 65-nm proof-of-concept integrated circuit, we measure 62 dB of in-band blocker rejection, while receiving up to four channels with independently defined locations anywhere up to 900 MHz.

A Mixer Front End for a Four-Channel Modulated Wideband Converter With 62-dB Blocker Rejection

Tri-state digital phase-frequency detectors (PFDs) are widely used for the large capture and locking range that they enable, but suffer from relatively large in-band phase noise. Sub-sampling phase detectors have recently been demonstrated to offer very low in-band noise but with only a very small capture range. We show how a PFD and a sub-sampling phase detector can be combined to maintain the phase-frequency detection capabilities while simultaneously obtaining in-band noise suppression. A 2.2GHz PLL is demonstrated in a 65nm CMOS process with an on-chip loop filter area of 0.04mm2. The measured in-band phase noise improves from −110dBc/Hz to −122dBc/Hz when the auxiliary sub-sampling phase detector is active.

A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression

A low-noise transconductance amplifier (LNTA) for wideband receivers based on a $g_{m} $ -boosted current mirroring topology that operates over 0.6- to 10.5-GHz is presented. $g_{m}$ boosting relaxes the $G_{m}$ and $S_{11} $ bandwidth (BW) tradeoff and the noise figure (NF) and input matching tradeoff. The active feedback synthesizes a second-order input impedance profile that further extends the $S_{11}$ BW. Despite the high $G_{m} $ obtained over large BW, high linearity is maintained through the predistortion inherent in the current mirroring topology. The LNTA is used in a 65-nm CMOS wideband channelizing iterative downconversion receiver targeting spectrum and signal analysis for cognitive radio and performs active signal splitting across two paths with a total postlayout simulated $G_{m} $ of 242 mS (170 and 72 mS in paths 1 and 2, respectively). $S_{11}$ BW and $G_{m} $ BW both exceed 10.5 GHz. Minimum LNTA NFs simulated in the two paths are 4 and 4.8 dB, respectively. Simulated wideband IIP3 and blocker P1dB are +6 and +1.5 dBm, respectively. Measurements of a direct conversion receiver in path 2 closely match simulations.

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Analysis and Design of a 0.6- to 10.5-GHz LNTA for Wideband Receivers

Circuits and methods for performing harmonic rejection mixing are provided. In some embodiments, the circuit comprises: a first amplifier that amplifies a received signal at a first gain; a second amplifier that amplifies the received signal at a fraction of the first gain; a mixer that receives a local oscillator signal having a first fundamental frequency and the first amplifier output, and outputs a first mixed signal; a second mixer that receives a second local oscillator signal having a fundamental frequency that is a multiple of the first fundamental frequency and the second amplifier output, and outputs a second mixed signal; and an output stage that receives the first and second mixed signals and outputs a sum of the first and second mixed signals.

Circuits and methods for performing harmonic rejection mixing

Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together.

Karthik Tripurari

Papers

A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

A 2.2GHz PLL using a phase-frequency detector with an auxiliary sub-sampling phase detector for in-band noise suppression

Analysis and Design of a 0.6- to 10.5-GHz LNTA for Wideband Receivers

Circuits and methods for performing harmonic rejection mixing

Circuits and methods for a combined phase detector