K
Kartik Mohanram
Researcher at University of Pittsburgh
Publications - 117
Citations - 3550
Kartik Mohanram is an academic researcher from University of Pittsburgh. The author has contributed to research in topics: Logic gate & Logic synthesis. The author has an hindex of 31, co-authored 117 publications receiving 3323 citations. Previous affiliations of Kartik Mohanram include Cisco Systems, Inc. & École Polytechnique Fédérale de Lausanne.
Papers
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Journal ArticleDOI
Gate sizing to radiation harden combinational logic
Quming Zhou,Kartik Mohanram +1 more
TL;DR: A gate-level radiation hardening technique for cost-effective reduction of the soft error failure rate in combinational logic circuits is described, which uses a novel gate (transistor) sizing technique that is both efficient and accurate.
Proceedings ArticleDOI
Cost-effective approach for reducing soft error failure rate in logic circuits
Kartik Mohanram,Nur A. Touba +1 more
TL;DR: A new paradigm for designing logic circuits with concurrent error detection (CED) based on partial duplication is described, capable of reducing the soft error failure rate significantly with a fraction of the overhead required for full duplication.
Journal ArticleDOI
Triple-mode single-transistor graphene amplifier and its applications.
TL;DR: A triple-mode single-transistor graphene amplifier utilizing a three-terminal back-gated single-layer graphene transistor, which offers new opportunities for designing analog circuits with simpler structure and higher integration densities for communications applications.
Proceedings ArticleDOI
High performance reliable variable latency carry select addition
TL;DR: An analytical model for the error rate of SCSA is developed to facilitate both design exploration and convergence and shows that on average, variable latency addition using SCSA-based speculative adders is 10% faster than the DesignWare adder with up to 43% area reduction.
Proceedings ArticleDOI
Partial error masking to reduce soft error failure rate in logic circuits
Kartik Mohanram,Nur A. Touba +1 more
TL;DR: A new methodology for designing logic circuits with partial error masking is described, which uses two reduction heuristics to reduce the soft error failure rate significantly with a fraction of the overhead required for conventional TMR.