Kathy Boucart

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.

TL;DR: In this article, the length scaling of the double gate tunnel field effect transistor (DG tunnel FET) is studied. And the authors demonstrate that while some improvements are observed, the length scale does not dramatically affect switch figures of merit such as subthreshold slope, Ion and I off, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET.

TL;DR: Reference NANOLAB-CONF-2005-019View record in Web of Science Record created on 2007-05-16, modified on 2017-05/10 as discussed by the authors.

TL;DR: In this article, the length scaling of the double gate tunnel field effect transistor (DG Tunnel FET) is studied. And the authors show that the scaling limits are reached sooner by tunnel FETs with an SiO2 gate dielectric, while those with a high-K dielectoric can be scaled further before threshold voltage, and average and point subthreshold swing are affected.

TL;DR: In this article, the authors report on the physical definition and extraction of threshold voltage in tunnel FETs (field effect transistors) based on numerical simulation data, and they show that the threshold voltage can be physically defined based on the transition between a quasiexponential dependence, and a linear dependence of the drain current on VGS or VDS, and by extension, on the saturation of the tunneling energy barrier width narrowing.