/pdf/convex-analysisnoer-san-nojin-zhan-nituite-5dl2rbmoyr.pdf

Convex Analysisの二,三の進展について

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

/pdf/a-survey-of-research-and-practices-of-network-on-chip-2rc0mlsrfq.pdf

A survey of research and practices of Network-on-chip

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best-effort services.

/pdf/aethereal-network-on-chip-concepts-architectures-and-1tugx9w8o1.pdf

AEthereal network on chip: concepts, architectures, and implementations

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

/pdf/performance-evaluation-and-design-trade-offs-for-network-on-2r2qk1xk70.pdf

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

http://www.es.ele.tue.nl/~kgoossens/2013-micpro.pdf

TeMNOT: A test methodology for the non-intrusive online testing of FPGA with hardwired network on chip

In this chapter, we analyze the factors that complicate the post-silicon debugging of a single SOC building block. In Sect. 2.1, we first introduce a formal finite state machine (FSM) description, to capture the cycle-accurate behavior of a single building block. To debug the silicon implementation of the corresponding building block, we can subsequently use the debug process described in Sect. 1.3 to compare its behavior to the behavior that is captured by this description. In doing so, we identify however six factors in Sect. 2.2 that complicate (the application of) this process. We conclude this chapter with a summary in Sect. 2.3.

Post-silicon Debugging of a Single Building Block

In the method and data processing system according to the invention the contents of a connection means are created using a single signaling means. In this manner, frequently used connections remain configured when the integrated circuit is in operation, and no time and resources are lost to set up these connections repeatedly. This concept is particularly advantageous if it is certain that these 'preset' connections are always used, and if at design-time it is clear that these connections will be set up frequently in the network. For example, a CPU module will certainly need a connection to a memory controller module, so it makes sense to (at least partially) set up this connection beforehand using a single signaling means. Furthermore, connections can be used from the controller unit to any of the network interlace units, in order to facilitate the configuration of connections at run-time.

Data processing system and method for configuring a network on an at least one integrated circuit

Future automotive systems, with Advanced Driving Assistance Systems and Autonomous Driving functionalities, will require fail-operational electronic systems. To achieve that, redundancy is a necessary technique, like in many other fields such as aviation. Moreover the applications have different safety requirements, from safety-critical related applications, for example for the driver replacement domain, to QoS-oriented applications, for example for the infotainment domain. Redundancy in mixed-criticality systems can be solved by physically separating system resources or by using isolated virtualized environments with e.g. hypervisors. There are costs associated to both solutions. In this work we describe a novel model we use to characterize a mixed-criticality automotive system and the analysis steps to obtain quantified metrics. The quantified metrics include cost, failure probability, total functional and communication loads, and total cable length, to compare the different solutions from a system-level perspective. We analyse the same set of mixed-criticality applications that represent a simplified automotive system in four scenarios. The architecture topology is either domain-based or zone-based, and we use either physical separation or virtualization to provide isolation. The obtained results show how the model and the analysis allows us to understand the trade-offs between the different solutions in specific applications scenarios, and how to vary the metrics used in the analysis to adapt to a different applications scenario.

Isolation of redundant and mixed-critical automotive applications: effects on the system architecture

In this paper, we describe and analyze the architecture of the proposed Debug Event Distribution Interconnect (EDI). The EDI transmits debug events, which are 1-bit signals, between debug entities in different areas of the Network-on-Chip based Multi-Processor System-on-Chip. The EDI replicates the NoC topology with an EDI node instantiated for each underlying NoC data module. Contention in the EDI node is handled by replicating the EDI in layers. The EDI generation is automatic, and uses as input the cross-triggering patterns that are not required to follow the communication patterns in the NoC. The generation and routing tool is also presented in this paper. The EDI is evaluated with four different implementations varying complexity and handling of contention. The area of a single EDI Layer is around 0.9% of the area occupied by the tested NoCs, using the lower area implementation. These results show that the proposed implementation of the EDI incurs low cost on the overall system.

/pdf/architecture-and-design-flow-for-a-debug-event-distribution-43njrsqzi4.pdf

Kees Goossens

Papers

TeMNOT: A test methodology for the non-intrusive online testing of FPGA with hardwired network on chip

Post-silicon Debugging of a Single Building Block

Data processing system and method for configuring a network on an at least one integrated circuit

Isolation of redundant and mixed-critical automotive applications: effects on the system architecture

Architecture and design flow for a debug event distribution interconnect