/pdf/convex-analysisnoer-san-nojin-zhan-nituite-5dl2rbmoyr.pdf

Convex Analysisの二,三の進展について

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

/pdf/a-survey-of-research-and-practices-of-network-on-chip-2rc0mlsrfq.pdf

A survey of research and practices of Network-on-chip

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best-effort services.

/pdf/aethereal-network-on-chip-concepts-architectures-and-1tugx9w8o1.pdf

AEthereal network on chip: concepts, architectures, and implementations

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

/pdf/performance-evaluation-and-design-trade-offs-for-network-on-2r2qk1xk70.pdf

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Design of real-time MPSoC systems including multiple applications is challenging because temporal requirements of each application must be respected throughout the entire design flow. Currently the design of different applications is often interdependent, making converge to a solution for each application difficult. This chapter proposes a compositional method to design applications independently, and then to execute them without interference. We define a formal modeling framework as a suitable entry point for application design. The models are executable, which enables early detection of specification errors, and include the formal properties of the applications based on well-defined models of computation. We combine this with a predictable MPSoC platform template that has a supporting design flow but lacks a simulation front-end. The structure and behavior of the application models are exported to an intermediate format via introspection which is iteratively transformed for the backend flow. We identify the problems arising in this transformation and provide appropriate solutions. The design flow is demonstrated by a system consisting of two streaming applications where less than half of the design time is dedicated to operating on the integrated system model.

/pdf/a-composable-and-predictable-mpsoc-design-flow-for-multiple-lop7kz8b22.pdf

A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications

The increasing number of applications implemented on modern vehicles leads to the use of multi-core platforms in the automotive field. As the number of I/O interfaces offered by these platforms is typically lower than the number of integrated applications, a solution is needed to provide access to the peripherals, such as the Controller Area Network (CAN), to all applications. Emulation and virtualization can be used to implement and share a CAN bus among multiple applications. In this article we present how multiple applications can share a CAN port, which can be on the local processor tile or on a remote tile. We evaluate our approach with four emulation and virtualization examples, trading the number of applications per core with the speed of the software emulated CAN bus.

Virtualization and emulation of a CAN device on a Multi-Processor System on Chip

In this paper we introduce the concepts of work of tokens (e.g. video frames) in an application, and slack arising from variations in work. Slack is used for dynamic voltage and frequency scaling in combination with a conservative power-management policy that never misses deadlines, for hard real-time applications, and with a non-conservative policy for soft real-time applications. We evaluate both policies for a number of different granularities (frequency of activation of the power manager) on an MPEG4 application, on energy and quality (deadline misses). We conclude that for soft real-time applications, there is a clear optimum in the energy, which depends on the work histogram of the application. The conservative policy has no deadline misses, and is only negligibly more expensive in terms of energy than the non-conservative policy. Finally, the granularity of both policies can be very coarse (128 frames) to reduce the power manager activation frequency, which has an insignificant energy cost.

/pdf/impact-of-power-management-granularity-on-the-energy-quality-1cpjlew7wp.pdf

Impact of power-management granularity on the energy-quality trade-off for soft and hard real-time applications

Design of real-time MPSoC systems including multiple applications is challenging because temporal requirements of each application must be respected throughout the entire design flow Currently the design of different applications is often interdependent, making converge to a solution for each application difficult This chapter proposes a compositional method to design applications independently, and then to execute them without interference We define a formal modeling framework as a suitable entry point for application design The models are executable, which enables early detection of specification errors, and include the formal properties of the applications based on well-defined models of computation We combine this with a predictable MPSoC platform template that has a supporting design flow but lacks a simulation front-end The structure and behavior of the application models are exported to an intermediate format via introspection which is iteratively transformed for the backend flow We identify the problems arising in this transformation and provide appropriate solutions The design flow is demonstrated by a system consisting of two streaming applications where less than half of the design time is dedicated to operating on the integrated system model

A composable and predictable MPSoC design flow for multiple real-time applications

This paper presents the Flex Tiles approach for the virtualization of hardware and software for a reconfigurable multicore architecture. The approach enables the virtualization of a dynamic tile-based hardware architecture consisting of processing tiles connected via a network-on-chip and a reconfigurable FPGA-based layer for application acceleration.

/pdf/hardware-software-virtualization-for-the-reconfigurable-120fxkmd21.pdf

Kees Goossens

Papers

A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications

Virtualization and emulation of a CAN device on a Multi-Processor System on Chip

Impact of power-management granularity on the energy-quality trade-off for soft and hard real-time applications

A composable and predictable MPSoC design flow for multiple real-time applications

Hardware / Software Virtualization for the Reconfigurable Multicore Platform