Showing papers by "Ken Mai published in 2013"

Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling

Abstract: With continued scaling of NAND flash memory process technology and multiple bits programmed per cell, NAND flash reliability and endurance are degrading. Understanding, characterizing, and modeling the distribution of the threshold voltages across different cells in a modern multi-level cell (MLC) flash memory can enable the design of more effective and efficient error correction mechanisms to combat this degradation. We show the first published experimental measurement-based characterization of the threshold voltage distribution of flash memory. To accomplish this, we develop a testing infrastructure that uses the read retry feature present in some 2Y-nm (i.e., 20-24nm) flash chips. We devise a model of the threshold voltage distributions taking into account program/erase (P/E) cycle effects, analyze the noise in the distributions, and evaluate the accuracy of our model. A key result is that the threshold voltage distribution can be modeled, with more than 95% accuracy, as a Gaussian distribution with additive white noise, which shifts to the right and widens as P/E cycles increase. The novel characterization and models provided in this paper can enable the design of more effective error tolerance mechanisms for future flash memories.

Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation

Abstract: As NAND flash memory continues to scale down to smaller process technology nodes, its reliability and endurance are degrading. One important source of reduced reliability is the phenomenon of program interference: when a flash cell is programmed to a value, the programming operation affects the threshold voltage of not only that cell, but also the other cells surrounding it. This interference potentially causes a surrounding cell to move to a logical state (i.e., a threshold voltage range) that is different from its original state, leading to an error when the cell is read. Understanding, characterizing, and modeling of program interference, i.e., how much the threshold voltage of a cell shifts when another cell is programmed, can enable the design of mechanisms that can effectively and efficiently predict and/or tolerate such errors. In this paper, we provide the first experimental characterization of and a realistic model for program interference in modern MLC NAND flash memory. To this end, we utilize the read-retry mechanism present in some state-of-the-art 2Y-nm (i.e., 20-24nm) flash chips to measure the changes in threshold voltage distributions of cells when a particular cell is programmed. Our results show that the amount of program interference received by a cell depends on 1) the location of the programmed cells, 2) the order in which cells are programmed, and 3) the data values of the cell that is being programmed as well as the cells surrounding it. Based on our experimental characterization, we develop a new model that predicts the amount of program interference as a function of threshold voltage values and changes in neighboring cells. We devise and evaluate one application of this model that adjusts the read reference voltage to the predicted threshold voltage distribution with the goal of minimizing erroneous reads. Our analysis shows that this new technique can reduce the raw flash bit error rate by 64% and thereby improve flash lifetime by 30%. We hope that the understanding and models developed in this paper lead to other error tolerance mechanisms for future flash memories.

A high reliability PUF using hot carrier injection based response reinforcement

Abstract: Achieving high reliability across environmental variations and over aging in physical unclonable functions (PUFs) remains a challenge for PUF designers. The conventional method to improve PUF reliability is to use powerful error correction codes (ECC) to correct the errors in the raw response from the PUF core. Unfortunately, these ECC blocks generally have high VLSI overheads, which scale up quickly with the error correction capability. Alternately, researchers have proposed techniques to increase the reliability of the PUF core, and thus significantly reduce the required strength (and complexity) of the ECC. One method of increasing the reliability of the PUF core is to use normally detrimental IC aging effects to reinforce the desired (or "golden") response of the PUF by altering the PUF circuit characteristics permanently and hence making the PUF more reliable. In this work, we present a PUF response reinforcement technique based on hot carrier injection (HCI) which can reinforce the PUF golden response in short stress times (i.e., tens of seconds), without impacting the surrounding circuits, and that has high permanence (i.e., does not degrade significantly over aging). We present a self-contained HCI-reinforcement-enabled PUF circuit based on sense amplifiers (SA) which autonomously self-reinforces with minimal external intervention. We have fabricated a custom ASIC testchip in 65nm bulk CMOS with the proposed PUF design. Measured results show high reliability across environmental variations and accelerated aging, as well as good uniqueness and randomness. For example, 1600 SA elements, after being HCI stressed for 125s, show 100% reliability (zero errors) across ±20% voltage variations a temperature range of -20°C to 85°C.

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states

Abstract: Physically Unclonable Functions (PUFs) are structures with many applications, including device authentication, identification, and cryptographic key generation. In this paper we propose a new PUF, called SCAN-PUF, based on scan-chain power-up states. We argue that scan chains have multiple characteristics that make them uniquely suited as a low-cost PUF. We present results from test chips fabricated in a 65nm bulk CMOS process in support of these claims. While approximately 20% of the total population of scan elements are unreliable across temperature variations, we find that simple unanimous selection schemes can result in mean error rates of less than 0.1% for the selected populations across all measurements collected.

Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC

Abstract: The embedded memory hierarchy of microprocessors and systems-on-a-chip plays a critical role in the overall system performance, area, power, resilience, and yield. However, as process technologies scale down to nanometer-regime geometries, the design and implementation of the embedded memory system are becoming increasingly difficult due to a number of exacerbating factors including increasing process variability, manufacturing defects, device wear out, and susceptibility to energetic particle strikes. Consequently, conventional memory resilience techniques will be unable to counter the raw bit error rate of the memory arrays in future technologies at economically feasible design points. Error correcting codes (ECC) are a widely-used and effective technique for correcting memory errors, but using conventional ECC techniques to correct more than one bit per word incurs high latency, area, and power overheads. In this work, we propose a novel ECC scheme based on erasure coding that can extend ECC to correct and detect multiple erroneous bits at low latency, area, and power overheads. Our results show that the increased memory resilience afforded by erasure-based ECC (EB-ECC) can be traded off to boost the memory performance, area, power, and yield. We show that EB-ECC, when combined with less than 5% row redundancy, can improve the cache access latency, power, and stability by over 40% on average, while maintaining near 100% yield and runtime reliability.