Showing papers by "Kern Rim published in 2006"

Laser surface annealing of antimony doped amorphized semiconductor region

Abstract: A sheet resistance stabilized recrystallized antimony doped region may be formed within a semiconductor substrate by annealing a corresponding antimony doped amorphized region at a temperature from about 1050° C. to about 1400° C. for a time period from about 0.1 to about 10 milliseconds. Preferably, a laser surface treatment is used. The laser surface treatment preferably uses a solid phase epitaxy. In addition, the antimony doped region may be co-doped with at least one of a phosphorus dopant and an arsenic dopant. The antimony dopant and the laser surface treatment lend sheet resistance stability that is otherwise absent when forming solely phosphorus and/or arsenic doped regions.

High performance stress-enhance mosfet and method of manufacture

Abstract: The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.

Silicon/silcion germaninum/silicon body device with embedded carbon dopant

Abstract: A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

Dual metal integration scheme based on full silicidation of the gate electrode

Abstract: An integration scheme that enables full silicidation (FUSI) of the nFET and pFET gate electrodes at the same time as that of the source/drain regions is provided. The FUSI of the gate electrodes eliminates the gate depletion problem that is observed with polysilicon gate electrodes. In addition, the inventive integration scheme creates different silicon thicknesses of the gate electrode just prior to silicidation. This feature of the present invention allows for fabricating nFETs and pFETs that have a band edge workfunction that is tailored for the specific device region.

CMOS process with Si gates for nFETs and SiGe gates for pFETs

Abstract: An integration scheme for providing Si gates for nFET devices and SiGe gates for pFET devices on the same semiconductor substrate is provided. The integration scheme includes first providing a material stack comprising, from bottom to top, a gate dielectric, a Si film, and a hard mask on a surface of a semiconductor substrate that includes at least one nFET device region and at least one pFET device region. Next, the hard mask is selectively removed from the material stack in the at least one pFET device region thereby exposing the Si film. The exposed Si film is then converted into a SiGe film and thereafter at least one nFET device is formed in the least one nFET device region and at least one pFET device is formed in the at least one pFET device region. In accordance with the present invention, the least one nFET device includes a Si gate and the at least one pFET includes a SiGe gate.

Optimized deep source/drain junctions with thin poly gate in a field effect transistor

Abstract: A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps and makes it possible to fabricate the structure without having dose loss or doping penetration problems. In accordance with the present invention, a sacrificial hard mask capping layer is used to block the high energy implantation and a 3-1 spacer (off-set spacer, first spacer and second spacer) scheme is used to optimize the source/drain doping profile. With this approach, the dose implanted into the thin poly-Si gate can be increased while the deep source/drain implantation can be optimized without worrying about the penetration problem.

Method for forming semiconductor structure comprising different species of silicide/germanide with cmos technique

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor structure comprising different species of silicide or germanide positioned in different regions of the semiconductor structure. SOLUTION: The different species of silicide or germanide is formed on a semiconductor layer and/or a conductor layer. By this invention, by utilizing combination of continuous accumulation of different metals and pattern formation, the different silicide or germanide are formed in the different regions of a semiconductor chip. This method includes a step for providing a Si-including layer or a Ge layer having at least a first region and a second region, a step for forming a first silicide or germanide in one of the first region and the second region, and a step for forming a second silicide or germanide having different composition from the first silicide or germanide in the other region not including the first silicide or germanide. The steps for forming the first and second silicide or germanide are performed continuously or with a single step. COPYRIGHT: (C)2007,JPO&INPIT

Transistor having stress-producing dielectric element underlying entire undersurface of active semiconductor region

Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a stress-producing dielectric element which underlies the entire undersurface of an active semiconductor region. SOLUTION: A compressive stress is applied to a channel region of a PFET by a structure including an independent stress-producing dielectric element that entirely underlies the bottom surface of an active semiconductor region in which a source, a drain and a channel region of the PFET are disposed. Specifically, the stress-producing dielectric element includes a region of a collapsed oxide which contacts the entire bottom surface of the active semiconductor region so that it has an area of the same spread as an area of the bottom surface. Bird beak-like oxide regions at the edges of the stress-producing dielectric element apply an upward force to the edges of the stress-producing dielectric element to provide a compressive stress to the channel region of the PFET. COPYRIGHT: (C)2007,JPO&INPIT