Dureseti Chidambarrao

TL;DR: In this article, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow, which results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current improvement of 11%/20%.

TL;DR: In this article, the impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors, and the impact of the design parameters are incorporated into parameters that measure predicted shift in mean oncurrent and mean offcurrent and parameters that measured predicted increase in deviations in the distribution of on current and the offcurrent.

TL;DR: In this article, the authors presented a physical contact tunneling model that is critical for studying the increasingly important contact behavior in future scaled CMOS. And they compared the performance of raised S/D and Schottky S/d MOSFETs.

TL;DR: In this paper, a substrate under tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas.

TL;DR: In this article, a SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component, which causes a compressive component in the pFET channel and a tensile component in nFET channels.