Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

Preface. About the Authors. Acknowledgments. 1 Power Amplifier Fundamentals. 1.1 Introduction. 1.2 Definition of Power Amplifier Parameters. 1.3 Distortion Parameters. 1.4 Power Match Condition. 1.5 Class of Operation. 1.6 Overview of Semiconductors for PAs. 1.7 Devices for PA. 1.8 Appendix: Demonstration of Useful Relationships. 1.9 References. 2 Power Amplifier Design. 2.1 Introduction. 2.2 Design Flow. 2.3 Simplified Approaches. 2.4 The Tuned Load Amplifier. 2.5 Sample Design of a Tuned Load PA. 2.6 References. 3 Nonlinear Analysis for Power Amplifiers. 3.1 Introduction. 3.2 Linear vs. Nonlinear Circuits. 3.3 Time Domain Integration. 3.4 Example. 3.5 Solution by Series Expansion. 3.6 The Volterra Series. 3.7 The Fourier Series. 3.8 The Harmonic Balance. 3.9 Envelope Analysis. 3.10 Spectral Balance. 3.11 Large Signal Stability Issue. 3.12 References. 4 Load Pull. 4.1 Introduction. 4.2 Passive Source/Load Pull Measurement Systems. 4.3 Active Source/Load Pull Measurement Systems. 4.4 Measurement Test-sets. 4.5 Advanced Load Pull Measurements. 4.6 Source/Load Pull Characterization. 4.7 Determination of Optimum Load Condition. 4.8 Appendix: Construction of Simplified Load Pull Contours through Linear Simulations. 4.9 References. 5 High Efficiency PA Design Theory. 5.1 Introduction. 5.2 Power Balance in a PA. 5.3 Ideal Approaches. 5.4 High Frequency Harmonic Tuning Approaches. 5.5 High Frequency Third Harmonic Tuned (Class F). 5.6 High Frequency Second Harmonic Tuned. 5.7 High Frequency Second and Third Harmonic Tuned. 5.8 Design by Harmonic Tuning. 5.9 Final Remarks. 5.10 References. 6 Switched Amplifiers. 6.1 Introduction. 6.2 The Ideal Class E Amplifier. 6.3 Class E Behavioural Analysis. 6.4 Low Frequency Class E Amplifier Design. 6.5 Class E Amplifier Design with 50# Duty-cycle. 6.6 Examples of High Frequency Class E Amplifiers. 6.7 Class E vs. Harmonic Tuned. 6.8 Class E Final Remarks. 6.9 Appendix: Demonstration of Useful Relationships. 6.10 References. 7 High Frequency Class F Power Amplifiers. 7.1 Introduction. 7.2 Class F Description Based on Voltage Wave-shaping. 7.3 High Frequency Class F Amplifiers. 7.4 Bias Level Selection. 7.5 Class F Output Matching Network Design. 7.6 Class F Design Examples. 7.7 References. 8 High Frequency Harmonic Tuned Power Amplifiers. 8.1 Introduction. 8.2 Theory of Harmonic Tuned PA Design. 8.3 Input Device Nonlinear Phenomena: Theoretical Analysis. 8.4 Input Device Nonlinear Phenomena: Experimental Results. 8.5 Output Device Nonlinear Phenomena. 8.6 Design of a Second HT Power Amplifier. 8.7 Design of a Second and Third HT Power Amplifier. 8.8 Example of 2nd HT GaN PA. 8.9 Final Remarks. 8.10 References. 9 High Linearity in Efficient Power Amplifiers. 9.1 Introduction. 9.2 Systems Classification. 9.3 Linearity Issue. 9.4 Bias Point Influence on IMD. 9.5 Harmonic Loading Effects on IMD. 9.6 Appendix: Volterra Analysis Example. 9.7 References. 10 Power Combining. 10.1 Introduction. 10.2 Device Scaling Properties. 10.3 Power Budget. 10.4 Power Combiner Classification. 10.5 The T-junction Power Divider. 10.6 Wilkinson Combiner. 10.7 The Quadrature (90 ) Hybrid. 10.8 The 180 Hybrid (Ring Coupler or Rat-race). 10.9 Bus-bar Combiner. 10.10 Other Planar Combiners. 10.11 Corporate Combiners. 10.12 Resonating Planar Combiners. 10.13 Graceful Degradation. 10.14 Matching Properties of Combined PAs. 10.15 Unbalance Issue in Hybrid Combiners. 10.16 Appendix: Basic Properties of Three-port Networks. 10.17 References. 11 The Doherty Power Amplifier. 11.1 Introduction. 11.2 Doherty's Idea. 11.3 The Classical Doherty Configuration. 11.4 The 'AB-C' Doherty Amplifier Analysis. 11.5 Power Splitter Sizing. 11.6 Evaluation of the Gain in a Doherty Amplifier. 11.7 Design Example. 11.8 Advanced Solutions. 11.9 References. Index.

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High Efficiency RF and Microwave Solid State Power Amplifiers

https://calhoun.nps.edu/bitstream/10945/24839/1/singlesidebandtr00elli.pdf

Single sideband transmission by envelope elimination and restoration.

In-band full-duplex (IBFD) technology can enable unique system capabilities and network architectures by allowing devices to transmit and receive on the same frequency at the same time. While previously considered impossible, this ability can now be used to optimize resource sharing within the crowded frequency spectrum for various communication systems, including 5G new radio. The potential of these IBFD systems can only be realized if each device incorporates a sufficient number of self-interference cancellation techniques to ensure that its receivers do not saturate. This tutorial survey offers the most comprehensive collection to date of these techniques and discusses how all of them can be implemented within the different domains of a typical transceiver. In addition, the results of a novel IBFD system study are presented for more than 50 demonstrated communication systems with more than 80 different measurement scenarios. The various system parameters are then combined into a new figure of merit, which can be used to propel future research and accelerate the inclusion of IBFD technology within an upcoming wireless standard.

In-Band Full-Duplex Technology: Techniques and Systems Survey

In-band full-duplex sets challenging requirements for wireless communication radios, in particular their capability to prevent receiver sensitivity degradation due to self-interference (transmit signals leaking into its own receiver). Previously published self-interference rejection designs require bulky components and/or antenna structures. This paper addresses this form-factor issue. First, compact radio transceiver feasibility bottlenecks are identified analytically, and tradeoff equations in function of link budget parameters are presented. These derivations indicate that the main bottlenecks can be resolved by increasing the isolation in analog/RF. Therefore, two design ideas are proposed, which provide attractive analog/RF-isolation and allow integration in compact radios. The first design proposal targets compact radio devices, such as small-cell base stations and tablet computers, and combines a dual-port polarized antenna with a self-tunable cancellation circuit. The second design proposal targets even more compact radio devices such as smartphones and sensor network nodes. This design builds on a tunable electrical balance isolator/duplexer in combination with a single-port miniature antenna. The electrical balance circuit can be implemented for scaled CMOS technology, facilitating low cost and dense integration.

Analog/RF Solutions Enabling Compact Full-Duplex Radios

This paper investigates electrical balance (EB) in hybrid junctions as a method of achieving transmitter-receiver isolation in single antenna full duplex wireless systems. A novel technique for maximizing isolation in EB duplexers is presented, and we show that the maximum achievable isolation is proportional to the variance of the antenna reflection coefficient with respect to frequency. Consequently, antenna characteristics can have a significant detrimental impact on the isolation bandwidth. Simulations that include embedded antenna measurements show a mean isolation of 62 dB over a 20-MHz bandwidth at 1.9 GHz but relatively poor performance at wider bandwidths. Furthermore, the operational environment can have a significant impact on isolation performance. We present a novel method of characterizing radio reflections being returned to a single antenna. Results show as little as 39 dB of attenuation in the radio echo for a highly reflective indoor environment at 1.9 GHz and that the mean isolation of an EB duplexer is reduced by 7 dB in this environment. A full duplex architecture exploiting EB is proposed.

/pdf/optimum-single-antenna-full-duplex-using-hybrid-junctions-3lgcegim54.pdf

Optimum single antenna full duplex using hybrid junctions

Transceiver architectures utilizing various self-interference suppression techniques have enabled simultaneous transmission and reception at the same frequency. This full-duplex wireless offers the potential for a doubling of spectral efficiency; however, the requirement for high transmit-to-receive isolation presents formidable challenges for the designers of full duplex transceivers. Electrical balance in hybrid junctions has been shown to provide high transmit- to-receive isolation over significant bandwidths. Electrical balance duplexers require just one antenna, and can be implemented on-chip, making this an attractive technology for small form factor devices. However, the transmit-toreceive isolation is sensitive to antenna impedance variation in both the frequency domain and time domain, limiting the isolation bandwidth and requiring dynamic adaptation. Various contributions concerning the implementation and performance of electrical balance duplexers are reviewed and compared, and novel measurements and simulations are presented. Results demonstrate the degradation in duplexer isolation due to imperfect system adaptation in user interaction scenarios, and requirements for the duplexer adaptation system are discussed.

/pdf/electrical-balance-duplexing-for-small-form-factor-4mhkcgyg0y.pdf

Electrical balance duplexing for small form factor realization of in-band full duplex

A methodology for the design of multichannel, wideband, highly efficient hybrid Class-J power amplifiers for fourth-generation (4G) communication transmitters is proposed. The design procedure is based on the automatic generation and evaluation of a vast number of output matching networks of the same topology but different dimensions, with respect to efficiency, output power, and linearity. The approach can find application in the management of the efficiency/linearity/bandwidth tradeoff in amplifier design. In this paper, two matching network architectures have been considered. One multistubbed network and a stepped-impedance microstrip line network. The approach has been validated through the design, simulation, and measurement of two power amplifiers realized using the aforementioned procedure. The first amplifier covers 1.6-2.2 GHz (31.6% fractional bandwidth) with 55%-68% drain efficiency at the 2-dB compression point and worst case adjacent channel power ratio (ACRP) and error vector magnitude (EVM) of - 21.8 dBc and 8.35%, respectively, over the bandwidth. The second covers 0.5-1.8 GHz (113% fractional bandwidth) with 50%-69% drain efficiency at the 2-dB compression point and worst case ACRP of - 27.5 dBc and EVM of 4.22%. Both amplifiers are based on a commercial, packaged 10-W GaN HEMT transistor.

Multichannel and Wideband Power Amplifier Design Methodology for 4G Communication Systems Based on Hybrid Class-J Operation

It is common practice to design multiway power dividers by interconnecting two-way power dividers. Transmission lines are used to link the two-way dividers. This paper investigates the performance of the interconnected power divider and the effects of the interconnecting transmission lines. In particular, it will be shown that the performance of multiway dividers constructed by interconnecting even-number-section two-way dividers deteriorates significantly as the number of output ports increases. The interconnecting lines can be used to improve the performance of such dividers.

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General Design of Multiway Multisection Power Dividers by Interconnecting Two-Way Dividers

A signal processor has an input terminal and an output terminal for use in a wireless transmitter, for generating a radio frequency signal suitable for transmission, either with or without further power amplification. The signal processor separates an input signal into first and second processing paths, the first processing path generating a pulse train signal which is a digitised envelope signal, and the second processing path comprising phase processing means operable to generate a constant envelope phase signal. An RF switch is operable to switch the phase signal by means of the pulse train signal.

Kevin A. Morris

Papers

Optimum single antenna full duplex using hybrid junctions

Electrical balance duplexing for small form factor realization of in-band full duplex

Multichannel and Wideband Power Amplifier Design Methodology for 4G Communication Systems Based on Hybrid Class-J Operation

General Design of Multiway Multisection Power Dividers by Interconnecting Two-Way Dividers

Signal processor for use with a power amplifier in a wireless circuit