Design of hardware efficient FIR filter: A review of the state-of-the-art approaches

High-speed optical interconnects are crucial for both high performance computing and data centers. High power consumption and limited device bandwidth have hindered the move to higher optical transmission speeds. Integrated optical transceivers in silicon photonics using pulse-amplitude modulation (PAM) are a promising solution to increase data rates. In this paper, we review recent progress in silicon photonics for PAM transmissions. Copyright (c) 2018 IOP. Personal use is permitted. For any other purposes, permission must be obtained from the IOP by emailing permissions@iop.org.

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Silicon photonic modulators for PAM transmissions

Silicon photonics has enormous potential for ultrahigh-capacity coherent optical transceivers. We demonstrate an in-phase and quadrature (IQ) modulator using silicon photonic traveling-wave modulators optimized for higher order quadrature amplitude modulation (QAM). Its optical and RF characteristics are studied thoroughly in simulation and experiment. We propose a system-orientated approach to optimization of the silicon photonic IQ modulator, which minimizes modulator-induced power penalty in a QAM transmission link. We examine the tradeoff between modulation efficiency and bandwidth for the optimal combination of modulator length and bias voltage to maximize the clear distance between adjacent constellation points. This optimum depends on baud rate and modulation format, as well as achievable driving voltage swing. Measured results confirm our prediction using the proposed methodology. Without precompensating bandwidth limitation of the modulator, net data rates up to 232 Gb/s (70 Gbaud 16-QAM) on single polarization are captured, indicating great potential for 400+ Gb/s dual-polarization transmission.

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Silicon Photonic IQ Modulators for 400 Gb/s and Beyond

Transistor sizing is one of the most critical parts of comparator design which has a significant influence on comparator specifications. This paper presents an optimum design of a double-tail latch comparator based on transistor sizing with a great certainty to reach the best possible design due to using Hspice (as a software simulator) linked with a heuristic algorithm. To achieve a low-power, high-speed, low offset and, small size comparator, the multi-objective inclined planes optimization and Hspice were linked and several Pareto-fronts were obtained. As a result of analyzing the Pareto-fronts, power and total sizes of transistors have a tradeoff with delay and offset voltage. Meanwhile, the results comparison with a recent work shows the superiority of the present approach performance.

Optimum design of a double-tail latch comparator on power, speed, offset and size

Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM’s Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC’s ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only.

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links.

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.

An improved low offset latch comparator for high-speed ADCs

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

Multistandard wireless communication systems require the reconfigurable FIR filters with low complexity architectures. The complexity of FIR filters is dominated by the coefficient multipliers. It is well known that partial product is an efficient technique to reduce the complexity of coefficient multipliers in high order FIR filters implementation. A new hardware efficient reconfigurable FIR filter architecture is proposed in this paper based on the proposed binary signed subcoefficient method. Using the proposed coefficient representation method, the hardware requirements for multiplexer units are reduced dramatically with respect to typical methods. FPGA synthesis results of the designed filter architecture show 33% and 27% reduction in the resources usage over previously reported two state of the art reconfigurable architectures.

A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications

A push–pull silicon photonic Mach–Zehnder modulator (MZM) driver is presented which uses a switched capacitor approach to generate a ∼2 V peak-to-peak differential 4-level pulse amplitude modulation (PAM-4) signal. The driver chip includes a Gray encoder and retiming flip-flops. The switched capacitor approach allows driving the lumped silicon photonic MZM with reduced power consumption compared with the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400 Gbit/s 802.3 Ethernet. The chip was fabricated using a 65 nm CMOS technology and flip-chipped on top of the silicon photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4 dB extinction ratio for a 36 Gbit/s (18 Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of 0.11 mm2 and consumes 236 mW from 1.2 to 2.4 V supply voltages. This corresponds to an energy efficiency of 6.55 pJ/bit including Gray encoder and retiming, or 5.37 pJ/bit for the driver circuit only.

Khosrov Dabbagh Sadeghipour

Papers

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links.

An improved low offset latch comparator for high-speed ADCs

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications

Driver circuit for a PAM-4 optical transmitter using 65 nm CMOS and silicon photonic technologies