Showing papers in "Analog Integrated Circuits and Signal Processing in 2014"
TL;DR: A new circuit for practical emulation of the memristor and its applications in Memristor-based digital modulation is experimentally investigated.
Abstract: Since its inception many proposals and attempts have been reported on using the memristor in digital signal processing (DSP) circuits. Memristor-based DSP applications are mainly focusing on improving the performance of memories and in realizing synapses in neural networks. In most of the reported applications the verification of the proposed DSP circuits is made using mathematical-based memristor models. In this paper a new circuit for practical emulation of the memristor and its applications in memristor-based digital modulation is experimentally investigated.
86 citations
TL;DR: Fractional-order differentiator and integrator topologies are introduced in this paper, which offer the benefits of resistorless realizations, electronic adjustment of their characteristics, and capability for operating in 0.5 V power supply voltage.
Abstract: Fractional-order differentiator and integrator topologies are introduced in this paper. They offer the benefits of resistorless realizations, electronic adjustment of their characteristics, and capability for operating in 0.5 V power supply voltage. These have been achieved through the employment of the concept of the Sinh-Domain filtering. The performance of the proposed blocks has been evaluated through the Analog Design Environment of the Cadence software, using MOS transistor models provided by the TSMC 180 nm process. As application example, the design of a Sinh-Domain chain for realizing the preprocessing of the Pan-Tomkins algorithm has been given, where the conventional differentiator has been substituted by a fractional-order differentiator.
51 citations
TL;DR: A complexity-reduced Volterra series model for radio frequency power amplifier (PA) behavioral modeling and digital predistortion (DPD) allows for a substantial reduction in the requirements for digital signal processors and the time needed to construct and implement the DPD in a real-time environment.
Abstract: This paper expounds a complexity-reduced Volterra series model for radio frequency power amplifier (PA) behavioral modeling and digital predistortion (DPD). An analysis was conducted, which took into account the memory effect mechanisms of the PA. This led to a closed-form expression that relates the memoryless behavior of the PA to the finite impulse response feedback filter, which approximates the memory effects’ behavior. The analysis resulted in a complexity-reduced Volterra series model which allows for a substantial reduction in the requirements for digital signal processors and the time needed to construct and implement the DPD in a real-time environment. The proposed model was validated as a behavioral model and a DPD using two different PA architectures, employing two different transistor technologies, driven by both 20 MHz 1001 wideband code division multiple access and long term evolution signals. The results obtained demonstrate the excellent modeling and linearization capability of the complexity-reduced Volterra series model.
45 citations
TL;DR: A novel low voltage and low power single-CCII bootstrap circuit specifically designed to be implemented as input stage in ElectroCardio graphy (ECG) or ElectroEncephaloGraphy (EEG) acquisition systems, suitable for portable applications.
Abstract: In this letter we propose a novel low voltage and low power single-CCII bootstrap circuit specifically designed to be implemented as input stage in ElectroCardioGraphy (ECG) or ElectroEncephaloGraphy (EEG) acquisition systems. The proposed circuit implements only a second generation current conveyor that has been designed to obtain, at X and Z nodes, reduced parasitic impedances, so improving CCII performance. Moreover, simulation results are also presented for a two electrodes ECG system. The circuit, designed in a standard 0.35 μm CMOS technology, shows low voltage (1.5 V) low power (28 μW) characteristics, so it is particularly suitable for portable applications.
40 citations
TL;DR: In this article, a 0.25-V supplied bulk-driven symmetrical OTA implemented in 130nm CMOS process is presented, which can benefit from the voltage reduction and high linearity enabled by halo-implanted transistors.
Abstract: This paper presents a 0.25-V supplied bulk-driven symmetrical OTA implemented in 130-nm CMOS process. By operating in weak inversion, and using a distributed layout approach, the OTA can benefit from the voltage reduction and high linearity enabled by halo-implanted transistors. The proposed circuit consumes only 10-nW, features a low transconductance of 22-nS, and a total harmonic distortion of 0.53 % for a 100-mVpp input voltage, thus making it suitable for low-frequency and low-power $$G_m$$ G m -C applications.
36 citations
TL;DR: In this paper, an interesting oscillator solution derived from LC Colpitts circuit structure is presented, where the current gain of the current amplifier is utilized for driving oscillation condition together with two transconductances in frame of voltage differencing transconductance amplifier for adjusting of frequency of oscillation.
Abstract: The paper deals with an interesting oscillator solution derived from LC Colpitts circuit structure. Electronically controllable current gain of the current amplifier is utilized for driving of oscillation condition together with two transconductances in frame of voltage differencing transconductance amplifier for adjusting of frequency of oscillation. In the proposed structure these elements replace common bipolar transistor and metal coil. Designed circuit offers important advantages, i.e. absence of metal coil, quadrature outputs, amplitudes of generated signals independent of tuning process, linear electronic control of oscillation frequency (independent of oscillation condition). Implementation of circuit for amplitude stabilization and automatic control of oscillation condition for designed circuit is simple. These benefits are not available in classical LC Colpitts structures or in many well-known third-order oscillators. The theoretical conclusions are supported by experiments with behavioral representation employing commercially available devices and also by simulations using CMOS model.
34 citations
TL;DR: A single-stage multi-path operational amplifier for fast-settling switched-capacitor circuits is presented that significantly improves the DC gain, unity-gain bandwidth, and slew rate compared to the conventional folded-cascode amplifier.
Abstract: In this paper, a single-stage multi-path operational amplifier for fast-settling switched-capacitor circuits is presented. The proposed amplifier uses all idle devices in the conventional folded-cascode amplifier in the signal path and the positive feedback cross-coupled transistors to enhance both the small-signal and large-signal parameters. It significantly improves the DC gain, unity-gain bandwidth, and slew rate compared to the conventional folded-cascode amplifier with the same power consumption and input parasitic capacitance. Extensive circuit level analysis and simulation results using a 90 nm CMOS technology are provided to evaluate the usefulness of the proposed amplifier.
29 citations
TL;DR: Results show that the proposed GA-BP scheme is more efficient and effective than BP algorithm, and the hybrid of two algorithm will improve the evolving speed of neural network.
Abstract: With the development of analog integrated circuits technology and due to the complexity, and various types of faults that occur in analog integrated circuits, fault detection is a new idea, has been studied in recent decades. In this paper a three amplifier state variable filter is used as circuit under test (CUT) and, a hybrid neural network is proposed for soft fault diagnosis of the CUT. Genetic algorithm (GA) has the powerful ability of searching the global optimal solution, and back propagation (BP) algorithm has the feature of rapid convergence on the local optima. The hybrid of two algorithm will improve the evolving speed of neural network. GA-BP scheme adopts GA to search the optimal combination of weights in the solution space, and then uses BP algorithm to obtain the accurate optimal solution quickly. Experiment results show that the proposed GA-BP scheme is more efficient and effective than BP algorithm.
25 citations
TL;DR: A particle swarm optimization is proposed to optimize the SVM to diagnose switched current circuits and it is shown that the method performs well in the part of fault diagnostic accuracy.
Abstract: This paper presents a new fault diagnosis method for switched current (SI) circuits. The kurtoses and entropies of the signals are calculated by extracting the original signals from the output terminals of the circuit. Support vector machine (SVM) is introduced for fault diagnosis using the entropies and kurtoses as inputs. In this technique, a particle swarm optimization is proposed to optimize the SVM to diagnose switched current circuits. The proposed method can identify faulty components in switched current circuit. A low-pass SI filter circuit has been used as test beached to verify the effectiveness of the proposed method. The accuracy of fault recognition achieved is about 97 % although there are some overlapping data when tolerance is considered. A comparison of our work with Long et al. (Analog Integr Circuit Signal Process 66:93---102, 2011), which only used entropy as a preprocessor, reveals that our method performs well in the part of fault diagnostic accuracy.
24 citations
TL;DR: In this paper, a new approach based on positive feedback is proposed to improve input impedances of the amplifiers, which is achieved by using only two extra transistors for each input.
Abstract: In this study, high-performance current-mode amplifiers Z-Copy current differencing buffered amplifier (ZC-CDBA) and current differencing trans-conductance amplifier (ZC-CDTA) are designed. In order to improve input impedances of the amplifiers, a new approach based on positive feedback is proposed. Impedance improvement/reduction is achieved by using only two extra transistors for each input. This number of extra transistors is very few compared to that in conventional negative feedback based improvement techniques. The proposed technique is justified by performing a detailed stability analysis. It is shown that the input impedances of ZC-CDBA and ZC-CDTA can be safely reduced to the level of 50 ? by considering fabrication scatterings. The proposed amplifiers are verified with analog filter applications, a new KHN and recently proposed biquadratic and frequency agile filters. It is shown that the filters operate accurately at the frequency level of 100 MHz. This is a clear sign of the proposed amplifiers' high performance. Layout and post layout simulations are done for the proposed circuits using AMS 0.18 µm parameters in Cadence environment.
22 citations
TL;DR: The proposed architecture significantly reduces the number of ADCs and I/O channels and hence drastically improves size, weight, area, power and cost of the system with minimal impact on receiver signal-to-noise ratios.
Abstract: We propose a novel transceiver architecture for cognitive sensing. The architecture supports agile beam forming, jamming mitigation, as well as MIMO communications. An essential aspect of the new architecture is its departure from the traditional digital beamforming approaches. Specifically, a single ADC is assigned to a group of array elements instead of having one ADC per element. To facilitate this approach, code division multiplexing is applied to each received antenna signal prior to combining them for digitization using a single ADC. Thus full signal recovery is possible at digital baseband via decoding. The proposed architecture significantly reduces the number of ADCs and I/O channels and hence drastically improves size, weight, area, power and cost of the system with minimal impact on receiver signal-to-noise ratios.
TL;DR: In this article, an updated version of the g m /I D -based sizing methodology for advanced short-channel CMOS technologies is presented, which can quickly and accurately size any linear analog circuit, top-down, from some required specifications and evaluate the remaining ones.
Abstract: This paper presents an updated version of the g m /I D -based sizing methodology for advanced short-channel CMOS technologies. The objective of this technique is to quickly and accurately size any linear analog circuit, top---down, from some required specifications and evaluate the remaining ones. A database describing the underlying MOS technology is taken as input of the sizing script, making the sizing process technology and corner independent. An advanced CMOS technology is analyzed, underlining the limitations of the original g m /I D methodology and its past improvements, then the proposed methodology is described in detail and tested successfully on a double stage amplifier, using two different CMOS technologies in all process-voltage-temperature corners.
TL;DR: Novel Log-Domain and Sinh-Domain integrators are introduced, where the realization of time-constants is achieved through a capacitor multiplication, and the performance of the derived filters has been evaluated through simulation and comparison results.
Abstract: Configurations of companding filters with large time-constants are presented in this paper. For this purpose, novel Log-Domain and Sinh-Domain integrators are introduced, where the realization of time-constants is achieved through a capacitor multiplication. The same concept has been followed in the case of realization of the Log-Domain and Sinh-Domain equivalents of passive elements. The performance of the derived filters has been evaluated through simulation and comparison results using the Analog Design Environment of the Cadence software and MOS transistors parameters provided by the TSMC 180 nm CMOS process. As a design example, a fourth-order bandpass filter has been realized for extracting the alpha, beta, gamma, and theta waves of an electroencephalogram.
TL;DR: In this paper, two methods are presented and detailed simulation results verifying the feasibility of the techniques are provided, in order to address the issue of poor tunability of integrated filters using MOS-only circuits.
Abstract: Although the design of integrated filters using MOS-only circuits provides some vital advantages, these circuits are inherently prone to have limited operating frequency range. This fact leads to a poor tunability range and seriously degrades the usefulness of this class of filters. In order to address this issue, two methods are presented and detailed simulation results verifying the feasibility of the techniques are provided.
TL;DR: In this paper, a high energy-efficiency switching scheme for low power successive approximation resister analogue-to-digital converter is proposed, which reduces the average switching energy and total capacitance of the proposed scheme by 97.7 and 87.5 % respectively compared to the conventional architecture.
Abstract: A high energy-efficiency switching scheme for low-power successive approximation resister analogue-to-digital converter is proposed. With sequence initialization, monotonic switching procedure and intermittent multiple references, the average switching energy and total capacitance of the proposed scheme are reduced by 97.7 and 87.5 % respectively compared to the conventional architecture. The applicability and superiority of the proposed scheme are proven by Matlab modeling and comparison with previous works.
TL;DR: In this paper, the authors developed an analytical method to determine the allowable range of LPF coefficient values by considering unified PLL specification constraints, and a clear guidance is obtained to facilitate LPF tuning and adaptive PLL design.
Abstract: To appropriately configure the low pass filter (LPF) coefficients plays an important role in determining phase locked loop circuit performance. Most phase locked loop (PLL) design methods calculate LPF coefficients based on preselected loop bandwidth, phase margin, and then adjust LPF parameters to meet other specification requirements, i.e. locking time and phase noise. Such design approaches typically involve a number of iterative simulations, which are time consuming and are not very efficient. In this paper, we develop an analytical method to determine the allowable range of LPF coefficient values by considering unified PLL specification constraints. With the range identified, a clear guidance is obtained to facilitate LPF tuning and adaptive PLL design. For model validation, a charge pump PLL is designed and simulated using a 3rd party PLL simulation program--Cppsim.
TL;DR: A field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools with a System-on-Chip template mapped on FPGA-based emulation systems that significantly accelerates the design process and characterization of highly optimized hardware modules.
Abstract: The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.
TL;DR: In this paper, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool.
Abstract: Systematic design methodologies for wireless transceivers require an efficient design of integrated inductors. Early availability of feasible trade-offs between inductance, quality factor, self-resonance frequency and area, is a key enabler towards the improvement of such design methodologies. This paper introduces such an approach in two steps. First, a Pareto-optimal performance front of integrated inductors is generated by embedding a performance evaluator into a multi-objective optimization tool. Then, starting from the optimal front samples, a surrogate model of the performance front is obtained. Experimental results in a 0.35-μm CMOS technology are provided.
TL;DR: In this article, the authors proposed a voltage differencing active building block for a multifunction frequency filter, which is based on the idea of the Akerberg-Mossberg (AM) filter, i.e. the integrators in the structure are always realized only by two active elements.
Abstract: The paper focuses on the application possibilities of the newly presented voltage differencing active building block called voltage differencing differential difference amplifier. Using this active element, a multifunction frequency filter is designed featuring the possibility of mutually independent control of quality factor Q and characteristic frequency $$\omega _0$$ ? 0 by means of active elements. The structure of the filter is based on the idea of the Akerberg-Mossberg (AM) filter, i.e. the integrators in the structure are always realized only by two active elements. This fact results in better phase compensation for the filter. Compared to the AM opamp based filter, the newly proposed structure features high-impedance inputs, low-impedance output, and all basic frequency responses. The performance of the proposed structure has been verified by SPICE simulations using the TSMC $$0.18\,\upmu \hbox {m}$$ 0.18 μ m level-7 SCN018 CMOS process parameters with $$\pm 0.9\,\hbox {V}$$ ± 0.9 V supply voltage.
TL;DR: In this article, a divide-by-4 injection-locked frequency divider (ILFD) was proposed and implemented in the TSMC 0.18 μm 1P6 M CMOS process.
Abstract: A novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in this paper and was implemented in the TSMC 0.18 μm 1P6 M CMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator with a parallel-tuned LC resonator and two mixers in series to serve as an injection device. At the drain-source bias of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-4 is 1.7 GHz, from the incident frequency 10.3---12.0 GHz, and the percentage of locking range is 15.25 %. The core power consumption is 11.98 mW. At drain-source voltage of 0.9 V, the locking range of the divide-by-4 is 2 GHz, from the incident frequency 10.1---12.1 GHz, and the percentage is 18.0 %. At drain-source voltage of 1.0 V, the locking range is 2.2 GHz (20.0 %) from 9.9 to 12.1 GHz. The die area is 0.492 × 0.819 mm2.
TL;DR: This paper presents an LED driver circuit architecture, incorporating analog and digital circuit blocks to deliver concurrent dimming control, and data transmission, and incorporates the feedback mechanisms to provide uniform light output together with the peak current control, which also prevents flickering.
Abstract: Recent breakthroughs in solid-state lighting technology have opened the door to a variety of applications using light-emitting diodes (LED's) for not only illumination, but also optical wireless communication. Low-power CMOS technology enables realization of system-on-chip driver circuits integrating multiple functions to control LED device performance, luminance, and data modulation for "intelligent" visible light networking. This paper presents an LED driver circuit architecture, incorporating analog and digital circuit blocks to deliver concurrent dimming control, and data transmission. This is achieved by independent control of output voltage and current using buck converter and current control loops, respectively. This integrated system incorporates the feedback mechanisms to provide uniform light output together with the peak current control, which also prevents flickering. The proposed architecture is flexible enough to take any digital base band modulation format. Designed and implemented in a 180 nm CMOS process, it provides linear 10---90 % dimming control while transmitting data. It also introduces a mechanism which can be applied to the off-the-shelf LED drivers and make them applicable for the visible light communication applications. The power consumption of on-chip circuitry, is negligible compared to the overall power consumption which yields an efficiency of 89 % at 120 mA of load current. The measured bit error rate (BER) varies from 10?6 at the data rate of 2.5 Mbps to 10?2 at the data rate of 7 Mbps. All control functions integrated on-chip with the total power consumption of 5 mW.
TL;DR: In this paper, two more 4-port mutator circuits, one with plus type (CCII+) and minus type current conveyors, and another with a plus type current follower (CF) are presented, their port relation matrix and their realization of different memstors are tabulated.
Abstract: In this paper, in addition to the universal 4-port mutator circuit introduced earlier with an adder and a subtractor block, two more 4-port mutator circuits, one with plus type (CCII+) and minus type current conveyors (CCII?), the other with a plus type current conveyor (CCII+) and one minus type current follower (CF?) are presented, their port relation matrix and their realization of different memstors are tabulated. How the transfer characteristics of the ideal mutative 4-ports with respect to frequency hold is verified using their transistor level simulations. By terminating properly two ports of the mutative 4-port simulations of a memristor with three different mutators, of a meminductor and of a memcapacitor are presented and compared also with some mutators existing in the literature.
TL;DR: In this article, a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology is presented, which includes fully differential preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits.
Abstract: This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8---32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.
TL;DR: In this article, a CMOS current-mode analog multiplier circuit based on a novel currentmode squarer circuit is proposed, which is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage.
Abstract: In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.
TL;DR: An area-efficient self-trimming technique for precision chopper-stabilized instrumentation amplifier (IA) is presented in this article, which uses a reconfigurable differential pair for the input stage and it is automatically configured to reduce the mismatch of the differential pair, suppressing the chopper ripple.
Abstract: An area-efficient self-trimming technique for precision chopper-stabilized instrumentation amplifier (IA) is presented. The amplifier uses a reconfigurable differential pair for the input stage and it is automatically configured to reduce the mismatch of the differential pair, suppressing the chopper ripple. To confirm the effectiveness of the proposed scheme, an IA with the complete calibration logic is fabricated in a standard 180-nm CMOS and achieves $$0.06 {-}\hbox{mm}^2$$ 0.06 - mm 2 active area, less than $$3.5 {-}\upmu \hbox{V}$$ 3.5 - μ V offset voltage, $$13.5 {-}\hbox{nV}/\surd \hbox {Hz}$$ 13.5 - nV / Â? Hz input-referred noise, and $$194 {-} \upmu \hbox {A}$$ 194 - μ A current consumption. The noise efficiency factor of the amplifier is 7.2.
TL;DR: To improve the budget link of the non-coherent based transceiver a Randomly Alternate OOK signaling is proposed which leads to an estimated communication range of 2.36 m in a free space propagation channel.
Abstract: This work presents a high rate UWB transceiver chipset implemented in a 130 nm CMOS technology for WBAN and biomedical applications in the 3---5 GHz band. The transmitter architecture is based on a double-filter excitation technique that can generate high magnitude pulses and address bipolar modulations such as BPSK. Measurements show that bipolar pulses with a peak-to-peak voltage of 1.9 Vpp for a power consumption of 139 µW@100 kbps can be generated. The receiver is a non-coherent architecture based on LNA followed by an envelope detector. A BER of 10?3 is achieved for a 3---5 GHz input peak-to-peak amplitude of 3.4 mVpp which corresponds to a ?89.3 dBm sensitivity at 100 kbps. The energy consumption of the receiver and of the transmitter is respectively 0.144 nJ/bit and 196 pJ/bit at 100 Mbps. To improve the budget link of our non-coherent based transceiver a Randomly Alternate OOK signaling is proposed which leads to an estimated communication range of 2.36 m in a free space propagation channel.
TL;DR: In this article, a floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented, which combines the exponential characteristics of MOS transistor in weak inversion, tunable property of FGMOS transistor, and its square law characteristic in strong inversion region to implement the GFG.
Abstract: In this paper floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented. The circuit combines the exponential characteristics of MOS transistor in weak inversion, tunable property of FGMOS transistor, and its square law characteristic in strong inversion region to implement the GFG. FGMOS based squarer is the core sub circuit of GFG that helps to implement full Gaussian function for positive as well as negative half of the input voltage. FGMOS implementation of the circuit provides low voltage operation, low power consumption, reduces the circuit complexity and increases the tunability of the circuit. The performance of circuit is verified at 0.75 V in TSMC 0.18 μm CMOS, BSIM3 and level 49 technology by using Cadence Spectre simulator. To ensure robustness of the proposed GFG, simulation results for various process corner variations have also been included.
TL;DR: In this paper, a common mode stability analysis of differential transformer-coupled CMOS mm-wave amplifiers with capacitive neutralization is investigated, and a robust common mode resistive stabilization technique is proposed to ensure complete stability of the amplifier.
Abstract: In this paper differential mode and common mode stability analysis of differential transformer-coupled CMOS mm-wave amplifiers with capacitive neutralization is investigated. Simulation of a differential amplifier implemented with a complete PSP transistor model shows that capacitive neutralization can improve the differential stability. In common mode however, the differential pair becomes potentially unstable over a wider frequency range. A robust common mode resistive stabilization technique, which ensures complete stability of the amplifier, is also discussed and analyzed. The analysis and stabilization techniques were successfully applied to stabilize a common mode unstable integrated F-band 45 nm CMOS amplifier. Measurements confirm the stabilization of the amplifier and a differential gain of 16 dB at 110 GHz is achieved.
TL;DR: The proposed solution method is an iterative procedure, with each iteration consisting of two phases, that finds the global minimum set of test points more accurately and more efficiently and is a good solution to optimize ATPS.
Abstract: Analog test point selection (ATPS) is an important problem that arises in the area of analog system testing. This paper formulates the problem as a combinatorial problem and proposes a solution method based on greedy randomized adaptive search procedure (GRASP). The proposed method is an iterative procedure, with each iteration consisting of two phases. The first phase, a construction phase, produces a feasible solution. The second, a local search, seeks for improvement on construction solution. In addition to applying the basic GRASP, the algorithm introduces randomness into both phases including: randomizing the selection of greedy criteria and checking redundant test points in a random order. The former can prevent the algorithm from converging prematurely to local optima, while the latter make the algorithm probably get more than one best solution. The efficiency of the proposed method is proven by two practical analog circuits as well as statistical experiments. Results show that our algorithm, compared with other methods, finds the global minimum set of test points more accurately and more efficiently. Therefore, it is a good solution to optimize ATPS.
TL;DR: In this paper, a 12th-order low voltage tunable differential complex filter for bluetooth and Zigbee applications is proposed based on improved controllable transconductors operating with the ultra-low supply voltage of 0.5 V. Simulation results using a triple-well 0.13 μm CMOS technology verify the filter operation fulfilling all the requirements for the complex filtering stage in bluetooth or Zigbee receivers.
Abstract: A 12th-order low voltage tunable differential complex filter for bluetooth and Zigbee applications is proposed in this paper. The filter is based on improved controllable transconductors operating with the ultra-low supply voltage of 0.5 V. Simulation results using a triple-well 0.13 μm CMOS technology verify the filter operation fulfilling all the requirements for the complex filtering stage in bluetooth or Zigbee receivers. The in-band group delay variation is 0.79 μs for bluetooth and 0.46 μs for Zigbee. The image rejection ratio is greater than 71 dB and the achieved in-band spurious free dynamic range is 42 dB.