Kiminobu Suzuki

TL;DR: A reference potential generating circuit according to this invention includes a first insulated gate field effect transistor of an enhancement type, a second insulated gate gate effect transistor, a depletion type and a voltage dividing circuit as discussed by the authors.

TL;DR: A layout-data generation equipment as discussed by the authors includes a logic circuit designing section which designs logic circuits based on information of the specifications of a semiconductor integrated circuit, a layout data generation section which creates layout data based on the logic circuits, a resistance information extraction section which extracts resistance information of a wire from the layout data, circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire, a verification section which verifies whether layout data of the wire breaks a design rule, the design rule being extracted from the information

TL;DR: In this article, a Bi-CMOS integrated circuit including an NPN-type (8, 15, 16) bipolar transistor, a P-MOS transistor (9, 17, 20), an N-mOS transistor, and a MOS transistor are formed on the same substrate.

TL;DR: In this paper, a design and optical proximity correction (OPC) flow with hybrid OPC and manufacturability check (MC) tool was found to be effective for making robust pattern formation without any hot spots within feasible lead time under the low-k1 lithography condition.

TL;DR: In this paper, a photomask is formed by combining a mask pattern and a SRAF (sub-resolution assist feature) pattern indicating the applicable region/non-applicable region of a redundant circuit in the mask forming device, which enables a mask inspection process to decide whether the redundant circuit is applicable or not, the decision conventionally carried out by a person.