IEEE transactions on very large scale integration (VLSI) systems

Multiplication is one of the most commonly used operations in the arithmetic Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication A number of modifications are proposed in the literature to optimize the area of the Wallace multiplier This paper proposed a reduced-area Wallace multiplier without compromising on the speed of the original Wallace multiplier Designs are synthesized using Synopsys Design Compiler in 90 nm process technology Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers The speed of the proposed and reference multipliers is almost the same

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Low-Area wallace multiplier

In recent years, Multiply-Accumulate (MAC) unit is developing for various high performance applications. MAC unit is a fundamental block in the computing devices, especially Digital Signal Processor (DSP). MAC unit performs multiplication and accumulation process. Basic MAC unit consists of multiplier, adder, and accumulator. In the existing MAC unit model, multiplier is designed using modified Radix-2 booth multiplier. In this paper, MAC unit model is designed by incorporating the various multipliers such as Array Multiplier, Ripple Carry Array Multiplier with Row Bypassing Technique, Wallace Tree Multiplier and DADDA Multiplier in the multiplier module and the performance of MAC unit models is analyzed in terms of area, delay and power. The performance analysis of MAC unit models is done by designing the models in Verilog HDL. Then, MAC unit models are simulated and synthesized in Xilinx ISE 13.2 for Virtex-6 family 40nm technology.

Design and performance analysis of Multiply-Accumulate (MAC) unit

Multiplier is main building block of all processor, which improves the speed of Digital Signal Processor (DSP). In special application in which we need to reduce the time delay. In proposed method, we design a Vedic multiplication algorithm by using Vedic mathematics formula Urdhava Tiryakbhyam method means vertically and cross wise. Vedic mathematics is mainly based on 16 Sutras and was rediscovered in early 20th century. In ancient time in India, people used this Sutra for decimal number multiplications effectively. The same basic concept of Vedic mathematics is applied to multiplication of binary number to make usable in the digital hardware system. The speed of the computation process is increased and the processing time is reduced due to decrease of combinational path delay compared to the existing multipliers. In our proposed multiplication algorithm, we get less time delay compared to other algorithms.[1]

High speed vedic multiplier used vedic mathematics

Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology that seems to suite well with signal-processing needs. It is concerned with great interest because of its benefits such as ultra-low power consumption, small size and can operate at one Terahertz. The multiply accumulator (MAC) unit is considered as one of the essential operations in digital signal processing (DSP). In the real-time DSP systems, several applications like speech processing, video coding, and digital filtering etc. require MAC operations. However, the power dissipation and area are the most significant aspects in these systems. Here, the authors design low power MAC unit based on QCA technology. QCADesigner version 2.0.3 is used to validate the accuracy of the proposed circuit. The reliability of this unit is taken at different temperatures. The power dissipation is estimated using QCAPro tool. The total power consumed by this unit is 2.183 μW. The proposed circuit has 90% improvement in terms of power over complementary metal–oxide–semiconductor (CMOS) circuits. Since the works in the field of QCA logic signal processing has started to progress, the suggested contribution will give rise to a new thread of research in the field of real-time signal and image treatment.

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

A design of high performance 64 bit Multiplier-and-Accumulator (MAC) is implemented in this paper. MAC unit performs important operation in many of the digital signal processing (DSP) applications. The multiplier is designed using modified Wallace multiplier and the adder is done with carry save adder. The total design is coded with verilog-HDL and the synthesis is done using Cadence RTL complier using typical libraries of TSMC 0.18um technology. The total MAC unit operates at 217 MHz. The total power dissipation is 177.732 mW.

Design of high performance 64 bit MAC unit

The clock distribution is important in all synchronous VLSI Design. The clock skew impacts the performance of synchronous logic circuits. As the scaling moves to nanometer technology, innovative clocking techniques are required to optimize the skew. This is done in backend process of design flow, (i.e.) skew is optimized in Pre and Post CTS. Here tunable clock buffers and tunable clock inverters is designed and it is compared. These designed buffers and inverters are useful for clock skew optimization in pre and post CTS.

Clock Skew Optimization in Pre and Post CTS

Objectives: This aim of this paper is to analyse different approaches for transient fault tolerance like PBS, RM-FT, FSP, BCE and MWFD. Methods: Transient faults are emerging as a critical issue in the reliability of real time systems. Besides multiprocessors being an apparent part of various booming technologies now-a-days, it becomes evident to make these systems susceptible, reliable and consistent to transient faults. Thus, to address the increasing susceptibility of multiprocessors systems to transient faults, different approaches are analysed to counter transient faults. Findings: To identify the optimal method for various constraints like slack time, reduction in time space and reconfiguration etc. Applications: This comparative analysis will help for us to identify the optimal approaches for tolerating the transient fault in critical real time systems.

Approaches for Transient Fault Tolerance in Multiprocessor - A State of Art

Sub threshold leakage current has increased dramatically with technology scaling and it consumes a significant portion of the total power. In order to reduce the leakage current, one of the efficient method is power gating. The main challenge in power gating is, to design switching fabric and power controller. In this paper the main aim is to implement power gating in semicustom design. For this we implement a power controller for the design, insert sleep transistors and size the sleep transistors. According to the input, the power controller generates the signal to decide which block is to turn ON and which one is to turn OFF. The switching transistors such as header or footer are inserted in to the design, which act as switches. Sizing of the sleep transistors is essential in order to reduce the long wake up delays. The proposed methodology is applied to 8 bit RISC architecture by using Design Architect from MENTOR GRAPHICS with the modified ADK library.

Kittur Harish Mallikarjun

Papers

Design of high performance 64 bit MAC unit

Clock Skew Optimization in Pre and Post CTS

Approaches for Transient Fault Tolerance in Multiprocessor - A State of Art

Semicustom power gating design