There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

An overview of sigma-delta converters

Recent studies demonstrated that dynamic spectrum access can improve spectrum utilization significantly by allowing secondary unlicensed users to dynamically share the spectrum that is not used by the primary licensed users. Cognitive radio was proposed to promote the spectrum utilization by opportunistically exploiting the existence of spectrum "holes." Meanwhile, cooperative relay technology is regarded widely as a key technology for increasing transmission diversity gain in various types of wireless networks, including cognitive radio networks. In this article, we first give a brief overview of the envisioned applications of: cooperative relay technology to CRNs, cooperative transmission of primary traffic by secondary users, cooperative transmission between secondary nodes to improve spatial diversity, and cooperative relay between secondary nodes to improve spectrum diversity. As the latter is a new direction, in this article we focus on this scenario and investigate a simple wireless network, where a spectrum-rich node is selected as the relay node to improve the performance between the source and the destination. With the introduction of cooperative relay, many unique problems should be considered, especially the issue for relay selection and spectrum allocation. To demonstrate the feasibility and performance of cooperative relay for cognitive radio, a new MAC protocol was proposed and implemented in a universal software radio peripheral-based testbed. Experimental results show that the throughput of the whole system is greatly increased by exploiting the benefit of cooperative relay.

/pdf/cooperative-relay-to-improve-diversity-in-cognitive-radio-1zzkfi7eo7.pdf

Cooperative relay to improve diversity in cognitive radio networks

An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

Fractional-N frequency synthesis using a phase locked loop (PLL) is considered. Advances in oversampling A/D conversion technology are incorporated into fractional-N synthesis, allowing the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier. Based on this new technology, a CMOS integrated fractional-N divider was successfully developed. A complete fractional-N PLL was constructed utilizing only a CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator (VCO). The resulting PLL exhibits no fractional spurs. >

A multiple modulator fractional divider

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.

/pdf/ring-amplifiers-for-switched-capacitor-circuits-51zowo08hc.pdf

Ring amplifiers for switched-capacitor circuits

A Stereo 16-Bit Delta-Sigma A/D Converter for Digital Audio

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

This paper describes a wideband high-linearity ?? ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled ?? ADC were realized in a 0.18-?m CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (SFDR>100 dB, THD=-98 dB) and an SNDR of 79 dB in a 4.2 MHz signal band.

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

In cascaded ΔΣ modulators (DSMs), the quantization noise of the earlier stage leaks to the output unless completely cancelled by the digital noise cancellation filter (NCF). The noise leakage is worse in the continuous-time (CT) implementation due to the poorly controlled time constant of the analog loop filter. A parameter-based continuous-time to discrete-time transform is developed to get an exact digital NCF, and the analog filter time constant is calibrated to match with the digital NCF. A binary pulse tone is injected into the quantizer to detect the filter time-constant error, and eliminated by zero-forcing its residual power based on the adaptive least-mean-square (LMS) algorithm. A 2-1-1 cascaded CT-DSM prototype in 0.18-μm CMOS demonstrates that the spectral density of the leaked noise is lower than 10 nV/?Hz after the capacitors in the Gm-C loop filters are trimmed with 1.1% step. With a 1-Vpp full-scale input, it achieves a dynamic range of 68 dB within 18-MHz bandwidth at an over-sampling ratio of 10. The analog core and the digital logic occupy 1.27 mm2,and consume 230 mW at 1.8 V.

Koichi Hamashita

Papers

Ring amplifiers for switched-capacitor circuits

A Stereo 16-Bit Delta-Sigma A/D Converter for Digital Audio

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators