Journal ArticleDOI
A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR
Kyehyung Lee,Jeongseok Chae,M. Aniya,Koichi Hamashita,K. Takasuka,S. Takeuchi,Gabor C. Temes +6 more
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TLDR
This paper describes a wideband high-linearity ADC that uses noise coupling combined with time interleaving to increase the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops.Abstract:
This paper describes a wideband high-linearity ?? ADC. It uses noise coupling combined with time interleaving. Two versions of a two-channel time-interleaved noise-coupled ?? ADC were realized in a 0.18-?m CMOS technology. Noise coupling between the channels increases the effective order of the noise-shaping loops, provides dithering, and prevents tone generation in all loops. Time interleaving enhances the effects of noise coupling. Using a 1.5 V supply, the device achieved excellent linearity (SFDR>100 dB, THD=-98 dB) and an SNDR of 79 dB in a 4.2 MHz signal band.read more
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Journal ArticleDOI
An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and $-$ 98 dB THD
TL;DR: A switched-capacitor low-distortion 15-level delta-sigma ADC achieves third-order noise shaping with only two integrators by using quantization noise coupling, which is among the best reported for discrete-time delta-Sigma ADCs in wideband applications.
Journal ArticleDOI
A Third-Order DT $\Delta\Sigma$ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer
Nima Maghari,Un-Ku Moon +1 more
TL;DR: This paper describes a new analog-to-digital converter based on the traditional dual-slope ADC operation that achieves first-order quantization noise shaping and a bi-directional discharging scheme is proposed to alleviate the speed of the counting-clock and the common-mode biasing accuracy requirements.
Journal ArticleDOI
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH $\Delta \Sigma$ Modulator Dissipating 16 mW Power
TL;DR: A new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area is presented and other changes are introduced to improve the modulators dynamic range (DR) and power dissipation.
Journal ArticleDOI
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC
TL;DR: In this paper, a hybrid delta-sigma/pipelined modulator is presented, which takes advantage of the high resolution and distributed pipelined quantization, and combines it with the noise shaping property of a delta sigma modulator.
Journal ArticleDOI
A 15-MHz Bandwidth 1-0 MASH $\Sigma \Delta $ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR
Seung-Chul Lee,Yun Chiu +1 more
TL;DR: A 1-0 MASH ΣΔ analog-to-digital converter (ADC) demonstrates a digital linearization technique for the first time treating integrator distortion with memory and capacitor mismatch errors and a two-tap sequential polynomial derived from an output-referred error analysis accurately models the non-ideality of a first-order modulator.
References
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Book
Understanding Delta-Sigma Data Converters
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Journal ArticleDOI
Time interleaved converter arrays
W.C. Black,David A. Hodges +1 more
TL;DR: In this article, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area.
Journal ArticleDOI
Wideband low-distortion delta-sigma ADC topology
TL;DR: In this paper, a /spl Delta/spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described, which is effective even for very low oversampling ratios, and can be used for any modulation order.
Journal ArticleDOI
Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging
R.T. Baird,Terri S. Fiez +1 more
TL;DR: A dynamic element matching algorithm, data weighted averaging, is introduced for use in multibit /spl Delta//spl Sigma/ data converters, resulting in a dynamic range improvement of 9 dB/octave when DAC errors dominate.
Journal ArticleDOI
Explicit analysis of channel mismatch effects in time-interleaved ADC systems
TL;DR: This paper derives explicit formulas for the mismatch effects when all of offset, gain and timing mismatches exist together in the time-interleaved ADC system and discusses the bandwidth mismatch effect.
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Wideband low-distortion delta-sigma ADC topology
Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging
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