Takashi Muto

TL;DR: A 100GbE gearbox LSI combining a 10:4 MUX and a 4:10 DEMUX — implemented in 65nm CMOS — decreases power dissipation by 75% compared to that of a conventional LSI.

TL;DR: In this article, an imaging apparatus outputs a first signal based on signal charge of a part of photoelectric conversion units of multiple photoelectric convert units, and a second signal based in the charge of multiple photometric conversion units.

TL;DR: Recently, there has been strong demand for high-resolution CMOS image sensors (large number of pixels) in the fields of security, science, and other specialized areas, and one of the major issues in realizing high- resolution image sensors is to speed up signal readout.

TL;DR: A 25Gb/s transceiver equalizing over 50dB channel loss is targeted, and a sub-mV dynamic DC offset cancelation and a decision-feedback equalizer (DFE) with a bias-controlled tap slicer are adopted to improve on the minimum input sensitivity and enable data transmission through a channel with over 50 dB loss.

TL;DR: In this paper, a sensor has an image sensing unit including pixel blocks, and a readout unit for reading out a signal from the image sensor via a second main electrode of the first transistor.