Korey Sewell

TL;DR: The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.

TL;DR: This work revisits the design of crossbar and high-radix interconnects in light of advances in circuit and layout techniques that improve crossbar scalability, obviating the need for deep multi-stage networks and employs the Swizzle-Switch, an energy and area-efficient switching element that has recently been validated via silicon test chips in 45 nm technology.

TL;DR: The challenges in scaling on-chip networks towards kilo-core processors are explored, and the best performing asymmetric high-radix topology improves average network latency over a mesh by 45% while reducing the power consumption by 40%.

TL;DR: The limit of voltage scaling together with task parallelization to maintain task completion latency is investigated and minimum task energy is obtained at “near threshold” supply-voltages across 6 commercial technology nodes and provides 4X improvement in overall CMP performance.

TL;DR: A 64x64 single-stage swizzle-switch network (SSN) with 128b data buses and an additional 4-level message-based priority arbitration for quality of service (QoS) with 2% logic and 3% wiring overhead, which results in a compact fabric.