K
Kwangho Lee
Researcher at Seoul National University
Publications - 15
Citations - 120
Kwangho Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Jitter & Adaptive equalizer. The author has an hindex of 5, co-authored 15 publications receiving 46 citations.
Papers
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Journal ArticleDOI
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference
TL;DR: The concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI).
Journal ArticleDOI
A 4–20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS
Kwanseo Park,Kwangho Lee,Sung-Yong Cho,Jinhyung Lee,Jeongho Hwang,Min-Seong Choo,Deog-Kyoon Jeong +6 more
TL;DR: A continuous-rate referenceless clock and data recovery (CDR) circuit with an unlimited frequency acquisition capability is presented and a frequency detector is derived from a multi-phase oversampling FD that achieves the unlimited frequency detection capability.
Journal ArticleDOI
A 2.44-pJ/b 1.62–10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE
TL;DR: This brief presents a 1.62-to-10-Gb/s receiver for next generation video interconnected with an adaptive decision-feedback equalizer (DFE) that facilitates the best bit error rate (BER) performance for various losses of video cables.
Proceedings ArticleDOI
A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler
TL;DR: This paper presents a forwarded-clock receiver that consists of a weight-adjusting sign-sign Mueller-Müller clock and data recovery and an adaptive decision-feedback equalizer with a single shared error sampler that minimizes clocking power consumption.
Journal ArticleDOI
An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter
TL;DR: An injection-locked phase-locked loop (ILPLL) which continuously tracks the injection timing to achieve improved jitter performance is presented and a calibration technique is proposed that continuously monitors the error information from the bang-bang phase and frequency detector when the injection of the reference clock is intentionally omitted every other cycle.