Kyungjun Cho

TL;DR: A deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs) that provides an optimal decap design that satisfies target impedance with a minimum area.

TL;DR: It is shown that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate and proposed concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s are proposed.

TL;DR: A novel hybrid loop array (HLA) for low leakage electromagnetic field (EMF) level and high efficiency in a wireless high power transfer system using kHz range resonant frequency is proposed.

TL;DR: Not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.

TL;DR: The proposed reinforcement learning-based optimal on-board decoupling capacitor (decap) design method has successfully provided 37 optimal decap designs with 4 decaps assigned each and satisfied the required target impedance while minimizing the number of assigned decaps.