다중혈관 관상동맥 환자에서 y-문합을 이용하여 양쪽 내흉동맥만을 사용한 우회술의 조기 성적

In this paper, we outline the historical evolution of RF and microwave design optimization and envisage imminent and future challenges that will be addressed by the next generation of optimization developments. Our journey starts in the 1960s, with the emergence of formal numerical optimization algorithms for circuit design. In our fast historical analysis, we emphasize the last two decades of documented microwave design optimization problems and solutions. From that retrospective, we identify a number of prominent scientific and engineering challenges: 1) the reliable and computationally efficient optimization of highly accurate system-level complex models subject to statistical uncertainty and varying operating or environmental conditions; 2) the computationally-efficient EM-driven multi-objective design optimization in high-dimensional design spaces including categorical, conditional, or combinatorial variables; and 3) the manufacturability assessment, statistical design, and yield optimization of high-frequency structures based on high-fidelity multi-physical representations. To address these major challenges, we venture into the development of sophisticated optimization approaches, exploiting confined and dimensionally reduced surrogate vehicles, automated feature-engineering-based optimization, and formal cognition-driven space mapping approaches, assisted by Bayesian and machine learning techniques.

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Advanced RF and Microwave Design Optimization: A Journey and a Vision of Future Trends

In this article, we cover the fundamentals of neural networks and Bayesian learning with a focus on signal and power integrity problems arising in packaging. Rather than only focus on mathematical formulations, we explain the important concepts and the intuition behind them, thereby demystifying the use of machine learning for these problems. We also share some of the recent developments in this area along with future research directions in the context of packaging. Links to open-source downloadable software for some of the methods discussed are also provided.

Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging

In this article, we first propose a deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs). The proposed method provides an optimal decap design that satisfies target impedance with a minimum area. Using deep RL algorithms based on reward feedback mechanisms, an optimal decap design guideline can be derived. For verification, the proposed method was applied to test power distribution networks (PDNs) and self-PDN impedance was compared with full search simulation results. We successfully verified by the full search simulation that the proposed method provides one of the solution sets. Conventional approaches are based on complex analytical models from power integrity (PI) domain expertise. However, the proposed method requires only specifications of the PDN structure and decap, along with a simple reward model, achieving fast and accurate data-driven results. Computing time of the proposed method was a few minutes, significantly reduced than that of the full search simulation, which took more than a month. Furthermore, the proposed deep RL method covered up to $10^{17}$ – $10^{18}$ cases, an approximately $10^{12}$ – $10^{13}$ order increase compared to the previous RL-based methods that did not utilize deep-learning techniques.

Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D/3-D ICs

As 4th industry revolution becomes realization, more sophisticated mobile sets and servers are demanded that, in turn, necessitates advanced package technologies. For mobile applications, Package on package (POP) and interposer POP have been widely used. When a laminate organic substrate is replaced by wafer level process, the electrical and thermal performances are greatly enhanced. However, a significant cost is added due to new wafer-level packaging equipment. For network systems and high-performance computing server applications perspective, a silicon interposer is increasingly adapted to integrate HBM (High-Bandwidth Memory) with various controller or logic devices. The merits of fine line and space design rule of silicon interposer cannot be found in any other package platforms. However, the silicon interposers suffer from costly TSVs and the lossy substrate which limits electrical performance. In this paper, three RDL based platforms (FO-PLP, FO-SIP and RDL Interposer) are introduced. An adequate platform can be chosen by considering package size (FO-PLP for mobile applications), thermal performance (FO-SIP for intelligent devices in near-future), competitive cost (RDL Interposer for servers as in consumer products). Nevertheless, RDL based platforms and 2.5D silicon interposer are not cannibalizing one another.

Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages

In this paper, for the first time, we designed and analyzed channels between a graphic processing unit and memory in a silicon interposer for a 3-D stacked high bandwidth memory (HBM). We thoroughly analyzed and verified the electrical characteristics of the silicon interposer considering various design parameters, such as the channel width and space, redistribution layer via, and under bump metallurgy pads. In particular, we also considered the meshed ground planes used for the proposed transmission lines, which are microstrip and strip lines. Signal integrity (SI) of the proposed channels in the silicon interposer was successfully analyzed and verified using a full 3-D electromagnetic solver and circuit simulations. Based on the extracted lumped circuit resistance, inductance, conductance and capacitance parameters, we thoroughly analyzed the channel characteristics and identified the parameters that dominantly affect SI in relation to each frequency range. From the analyzed insertion loss and far end crosstalk, we verified SI of the silicon interposer by eye-diagram simulations in terms of eye-height voltage and timing jitter in the time domain. In the worst case, the eye-height voltage and timing jitter of the proposed microstrip lines are 0.911 V and 36.8 ps, respectively, with 72 mV of signal coupling. The eye-height voltage and timing jitter of the proposed strip line are 0.887 V and 42.1 ps with 34 mV of single couplings. We show that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate. Finally, we propose concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s.

Signal Integrity Design and Analysis of Silicon Interposer for GPU-Memory Channels in High-Bandwidth Memory Interface

In this paper, for the first time, we propose a reinforcement learning-based optimal on-board decoupling capacitor (decap) design method. The proposed method can provide optimal decap designs for a given on-board power distribution network (PDN). An optimal decap design refers to the optimized combination of decaps at proper positions to satisfy a required target impedance. Moreover, a minimum number of decaps should be assigned for optimal decap designs. The proposed method is applied to the test on-board PDN and successfully provided 37 optimal decap designs with 4 decaps assigned each. Self impedance of PDN with the provided design satisfied the required target impedance while minimizing the number of assigned decaps.

Reinforcement Learning-Based Optimal on-Board Decoupling Capacitor Design Method

Electromagnetic interference (EMI) control is one of the most significant challenges for emerging consumer, automotive, Internet of things (IoT) and wearable systems. This paper demonstrates miniaturized and integrated nanostructures for component-level EMI isolation and external EMI shielding in ultra-miniaturized electronic systems. Multi-layered nanomagnetic and copper shielding materials are designed, synthesized, and characterized for their shielding effectiveness. Graphene is explored as an alternative EMI shield material. From the modeling and experimental analysis, the advantages of nanostructures for internal and external component-level shielding in different applications is discussed.

Highly-Effective Integrated EMI Shields with Graphene and Nanomagnetic Multilayered Composites

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

Subin Kim

Papers

Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D/3-D ICs

Signal Integrity Design and Analysis of Silicon Interposer for GPU-Memory Channels in High-Bandwidth Memory Interface

Reinforcement Learning-Based Optimal on-Board Decoupling Capacitor Design Method

Highly-Effective Integrated EMI Shields with Graphene and Nanomagnetic Multilayered Composites

Design and Analysis of Power Distribution Network (PDN) for High Bandwidth Memory (HBM) Interposer in 2.5D Terabyte/s Bandwidth Graphics Module