This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Introduction to flash memory

We report a new NBTI phenomenon for p-MOSFETs with ultra thin gate oxides. We demonstrate that in a CMOS inverter circuit, the interface traps generated under NBTI stressing in a p-MOSFET (corresponding to the "high" output state of the inverter) are subsequently passivated when the gate to drain voltage switches to positive (corresponding to the "low" output state of the inverter). As a result, it was found that this "Dynamic" NBTI (DNBTI) operating in a CMOS inverter circuit prolongs significantly the device lifetime while the conventional "static" NBTI (SNBTI) underestimates the device lifetime. Furthermore, the DNBTI effect is dependent on temperature and gate oxide thickness, but independent of operation frequency. A physical model is proposed for DNBTI that involves the interaction between hydrogen and silicon dangling bonds. This finding has significant impact on the determination of maximum operation voltage as well as lifetime projection for future scaling of CMOS devices.

Dynamic NBTI of PMOS transistors and its impact on device lifetime

Reliability- and process-variation aware design of integrated circuits.

Photoelectron spectroscopy studies of SiO2/Si interfaces

A unification of time-exponents for negative bias temperature instability (NBTI) and hot carrier injection (HCI) is established under the geometric interpretation of interface trap generation. Resolving the fundamental inconsistencies, a numerical reaction-diffusion (R-D) model that agrees with recent measurements is developed. The implications regarding the degradations of future sub-100 nm planar and surround-gate MOSFETs are presented.

A geometrical unification of the theories of NBTI and HCI time-exponents and its implications for ultra-scaled planar and surround-gate MOSFETs

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10/sup 4/ times more efficient in trap generation than the hot electron stress in terms of injected charge.

https://ir.nctu.edu.tw:443/bitstream/11536/32522/1/000074344100017.pdf

Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V/sub gs/ such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 /spl Aring/) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 /spl Aring/) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.

https://ir.nctu.edu.tw:443/bitstream/11536/31102/1/000082242500010.pdf

A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs

Enhanced hot carrier degradation with stress V/sub g/ in the valence-band tunneling regime is observed. This degradation is attributed to channel hole creation by valence-band electron tunneling. The created holes provide for Auger recombination with electrons in the channel and thus increase hot electron energy. The valence-band tunneling enhanced hot carrier degradation becomes more serious as gate oxide thickness is reduced. In ultrathin gate oxide nMOSFETs, our result shows that the valence-band tunneling enhanced degradation, as opposed to max. I/sub b/ stress induced degradation, exhibits positive dependence on substrate bias. This phenomenon may cause a severe reliability issue in positively biased substrate or floating substrate devices.

https://ir.nctu.edu.tw:443/bitstream/11536/19188/1/000166855900032.pdf

Valence-band tunneling enhanced hot carrier degradation in ultrathin oxide nMOSFETs

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant.

/pdf/characterization-of-various-stress-induced-oxide-traps-in-4m9pz6ih6f.pdf

Characterization of various stress-induced oxide traps in MOSFET's by using a subthreshold transient current technique

Enhanced hot carrier degradation is observed in DTMOS-like operation mode. This phenomenon is attributed to Auger recombination assisted hot electron process. Measured hot electron gate current and light emission spectrum in nMOSFETs provide evidence that the high-energy tail of channel electrons is increased by the application of a positive substrate bias. As opposed to conventional hot carrier degradation, the Auger enhanced degradation exhibits positive temperature dependence and is more significant at low drain bias.

https://ir.nctu.edu.tw:443/bitstream/11536/19276/1/000088359300052.pdf

L.P. Chiang

Papers

Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique

A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs

Valence-band tunneling enhanced hot carrier degradation in ultrathin oxide nMOSFETs

Characterization of various stress-induced oxide traps in MOSFET's by using a subthreshold transient current technique

Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias