This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Introduction to flash memory

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitride-oxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

Overview of candidate device technologies for storage-class memory

Storage-class memory (SCM) combines the benefits of a solidstate memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitrideoxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

https://researcher.watson.ibm.com/researcher/files/us-gwburr/NVMcandidates_IBMJRD.pdf

Overview of candidate device technologies for storage-class

Graphene’s single atomic layer of sp2 carbon has recently garnered much attention for its potential use in electronic applications. Here, we report a memory application for graphene, which we call graphene flash memory (GFM). GFM has the potential to exceed the performance of current flash memory technology by utilizing the intrinsic properties of graphene, such as high density of states, high work function, and low dimensionality. To this end, we have grown large-area graphene sheets by chemical vapor deposition and integrated them into a floating gate structure. GFM displays a wide memory window of ∼6 V at significantly low program/erase voltages of ±7 V. GFM also shows a long retention time of more than 10 years at room temperature. Additionally, simulations suggest that GFM suffers very little from cell-to-cell interference, potentially enabling scaling down far beyond current state-of-the-art flash memory devices.

Graphene flash memory.

Data retention loss mechanisms in a 2-bit SONOS type flash EEPROM cell with hot electron programming and hot hole erase are investigated. In erase (low-Vt) state, a threshold voltage drift with storage time is observed after P/E cycling stress. Positive trapped charge creation in the bottom oxide is found to be responsible for the drift. In program (high-Vt) state, data retention loss is attributed mostly to nitride charge escape by Frenkel-Poole emission and oxide trap assisted tunneling. A square-root dependence of the nitride charge loss on electric field is obtained. A Vg-acceleration method for retention lifetime measurement is proposed.

Data retention behavior of a SONOS type two-bit storage flash memory cell

Data retention loss in a localized trapping storage flash memory cell with a SONOS type structure is investigated. Both charge loss through the bottom oxide and lateral migration of trapped charges in the nitride layer are considered for the data retention loss. Charge pumping and charge separation methods are used in this study. Our results reveal that in normal operation condition the retention loss is mainly caused by charge leakage via P/E stress created oxide traps.

Cause of data retention loss in a nitride-based localized trapping storage flash memory cell

The reliability issues of two-bit storage nitride flash memory cells, including low-V/sub t/ state threshold voltage instability, read-disturb, and high-V/sub t/ state charge loss are addressed The responsible mechanisms and reliability models are discussed Our study shows that the cell reliability is strongly dependent on operation methods and process conditions

Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10/sup 4/ times more efficient in trap generation than the hot electron stress in terms of injected charge.

https://ir.nctu.edu.tw:443/bitstream/11536/32522/1/000074344100017.pdf

Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique

Over erasure, charge gain in the low Vt state, and charge loss in the high Vt state are found to be the most severe reliability issues in a localized trapping storage flash memory cell In this paper, based on our understanding of physical mechanisms, we demonstrate that by adding vertical electrical field treatments during program/erase operations, the over erasure and data retentivities in high/low Vt states are significantly improved

N.K. Zous

Papers

Data retention behavior of a SONOS type two-bit storage flash memory cell

Cause of data retention loss in a nitride-based localized trapping storage flash memory cell

Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

Investigation of oxide charge trapping and detrapping in a MOSFET by using a GIDL current technique

Novel operation schemes to improve device reliability in a localized trapping storage SONOS-type flash memory