We will review some of the major results in random graphs and some of the more challenging open problems. We will cover algorithmic and structural questions. We will touch on newer models, including those related to the WWW.

Random graphs

This document provides updates to IEEE Std 802.16's MIB for the MAC, PHY and asso- ciated management procedures in order to accommodate recent extensions to the standard.

IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems Draft Amendment: Management Information Base Extensions

No wonder you activities are, reading will be always needed. It is not only to fulfil the duties that you need to finish in deadline time. Reading will encourage your mind and thoughts. Of course, reading will greatly develop your experiences about everything. Reading invisible colleges diffusion of knowledge in scientific communities is also a way as one of the collective books that gives many advantages. The advantages are not only for you, but for the other peoples with those meaningful benefits.

Invisible colleges : diffusion of knowledge in scientific communities

Since the late 1980s there have been spectacular developments in micromechanical or microelectro-mechanical (MEMS) systems which have enabled the exploration of transduction modes that involve mechanical energy and are based primarily on mechanical phenomena. As a result an innovative family of chemical and biological sensors has emerged. In this article, we discuss sensors with transducers in a form of cantilevers. While MEMS represents a diverse family of designs, devices with simple cantilever configurations are especially attractive as transducers for chemical and biological sensors. The review deals with four important aspects of cantilever transducers: (i) operation principles and models; (ii) microfabrication; (iii) figures of merit; and (iv) applications of cantilever sensors. We also provide a brief analysis of historical predecessors of the modern cantilever sensors.

Cantilever transducers as a platform for chemical and biological sensors

Nanotechnology is the science of understanding matter and the control of matter at dimensions of 100 nm or less. Encompassing nanoscale science, engineering, and technology, nanotechnology involves imaging, measuring, modeling, and manipulation of matter at this level of precision. An important aspect of research in nanotechnology involves precision control and manipulation of devices and materials at a nanoscale, i.e., nanopositioning. Nanopositioners are precision mechatronic systems designed to move objects over a small range with a resolution down to a fraction of an atomic diameter. The desired attributes of a nanopositioner are extremely high resolution, accuracy, stability, and fast response. The key to successful nanopositioning is accurate position sensing and feedback control of the motion. This paper presents an overview of nanopositioning technologies and devices emphasizing the key role of advanced control techniques in improving precision, accuracy, and speed of operation of these systems.

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A Survey of Control Issues in Nanopositioning

The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented. >

/pdf/koan-anagram-11-new-tools-for-device-level-analog-placement-zl3r88czzf.pdf

KOAN/ANAGRAM 11: New Tools for Device-Level Analog Placement and Routing

This article describes an approach for implementing a complete computer system (CPU, RAM, I/O, and nonvolatile mass memory) on a single integrated-circuit substrate (a chip)—hence, the name “single-chip computer.” The approach presented combines advances in the field of microelectromechanical systems (MEMS) and micromagnetics with traditional low-cost very-large-scale integrated circuit style parallel lithographic manufacturing. The primary barrier to the creation of a computer on a chip is the incorporation of a high-capacity [many gigabytes (GB)] re-writable nonvolatile memory (in today’s terminology, a disk drive) into an integrated circuit (IC) manufacturing process. This article presents the following design example: a MEMS-based magnetic memory that can store over 2 GB of data in 2 cm2 of die area and whose fabrication is compatible with a standard IC manufacturing process.

Single-chip computers with microelectromechanical systems-based magnetic memory (invited)

High-speed medium-resolution ADCs are widely utilized in high-speed communication systems, such as serial links, UWB, and OFDM-based 60GHz receivers. Due to complex DSP and low-power constraints, digital basebands are designed in low-leakage, high-V T low-power (LP) CMOS processes making the design of high-speed ADCs challenging. Time-Interleaved (TI) Successive-Approximation-Register-based (SAR) ADCs[1] are ideally suited to these applications due to their highly scalable architecture and due to the steady improvement in matching and density of Metal-Finger Capacitors (MFC). This paper presents a TI C-2C SAR ADC that achieves high performance by using: 1) a small-area C-2C SAR architecture with low input capacitance; 2) high-speed boosted switches to overcome high device threshold; 3) background comparator offset calibration and radix calibration; and 4) redundant-ADC-based gain, offset and timing calibration to reduce TI errors.

A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

The device (10) is comprised of a cantilevered beam (22, 58) positioned above, and free to move relative to, a substrate (24). The beam (22) may carry a plurality of conductors (44, 50) which are insulated from one another. One or more tips (28) is positioned on the beam with each tip being in electrical contact with one of the conductors. A memory device may be constructed by providing an array of such cantilevered beams proximate to a layer of media (16). Devices for positioning the beam in x and y directions (30, 32, 34, 36) perpendicular to each other and parallel to the layer of media and in a z direction (26, 68, 70) perpendicular to the media are provided. A control circuit (14) generates control signals input to the positioning devices for positioning the tips according to x, y and z coordinates. A read/write circuit (14) which is in electrical communication with the conductors of the beam, provide signals to the tips to cause the tips to write those signals to the layer of media in a write mode and to read previously written signals sensed by the tips in a read mode. A fabrication method is also disclosed.

Microelectromechanical structure and process of making same

The increasing availability of dynamically growing digital data that can be used for extracting social networks has led to an upsurge of interest in the analysis of dynamic social networks. One key aspect of social network analysis is to understand the central nodes in a network. However, dynamic calculation of centrality values for rapidly growing networks might be unfeasibly expensive, especially if it involves recalculation from scratch for each time period. This paper proposes an incremental algorithm that effectively updates betweenness centralities of nodes in dynamic social networks while avoiding re-computations by exploiting information from earlier computations. Our performance results suggest that our incremental betweenness algorithm can achieve substantial performance speedup, on the order of thousands of times, over the state of the art, including the best-performing non-incremental betweenness algorithm and a recently proposed betweenness update algorithm.

/pdf/incremental-algorithm-for-updating-betweenness-centrality-in-4i1pnfcnlv.pdf

L. Richard Carley

Papers

KOAN/ANAGRAM 11: New Tools for Device-Level Analog Placement and Routing

Single-chip computers with microelectromechanical systems-based magnetic memory (invited)

A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

Microelectromechanical structure and process of making same

Incremental algorithm for updating betweenness centrality in dynamically growing networks