Laurent Artola

TL;DR: In this article, the analog performance as well as some new RF figures of merit are reported for the first time of a gate stack double gate (GS-DG) metal oxide semiconductor field effect transistor (MOSFET) with various gates and channel engineering.

TL;DR: The results suggest muon-induced upset affects the soft error rate from 32-nm SRAM operated at a nominal supply voltage and has a significant impact for circuits fabricated in smaller process technologies (22-nm and 14-nm).

TL;DR: In this paper, the relative contribution of the radial ionization profile on SEE prediction is investigated using MUSCA-SEP3, in comparison with the classical approach considering the ion track as a series of punctual charges.

TL;DR: In this article, a SET predictive methodology based on coupled MUSCA SEP3 and electrical simulations (CADENCE tool) is presented, validated by SET measurements on an inverters chain based on 65-nm bulk CMOS technology, and two designs were considered (respectively for same-well and separatewell designs).

TL;DR: In this article, a new methodology of prediction for SEU based on SET modeling is proposed based on the ADDICT model for predicting single event transients and upsets in bulk transistors and SRAMs down to 65 nm.