A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.

Characterization adn reduction of variation for integrated circuits

Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process includes lithography or etch. Predicted characteristics are verified to conform to the design, the characteristics including feature dimensions or electrical characteristics. A process is selected for use in fabricating the integrated circuit based on the relative predicted variations. Chip-level features of a design of an integrated circuit are verified for manufacture within focus limitations of a lithographic tool. Whether a design of a level of an integrated circuit can be lithographically imaged in accordance with the design is predicted, and if it cannot be, the design or processing parameters are adjusted so that it can be.

Characterization and verification for integrated circuit designs

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Dummy fill for integrated circuits

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information regarding defect printability. Certain other aspects of the mask relating to mask quality, such as line edge roughness and contact corner rounding, can also be quantified by using the simulated wafer image of the physical mask.

System and method of providing mask defect printability analysis

Mask simulation tools are typically extremely complicated to learn and to use effectively. Therefore, providing access to a mask simulation tool over a wide area network (WAN) to multiple on-line users can be very cost effective. Specifically, in a network-based simulation server, multiple users can view the same mask image, simulations, and analysis results and provide real-time comments to each other as simulation and analysis are performed, thereby encouraging invaluable problem-solving dialogue among users. The user interface for this mask simulation tool can advantageously facilitate this dialogue. For example, the user interface can include an enter box for a user to enter a message and a talk box for capturing any message sent by any user of the simulation tool using the enter box.

User interface for a networked-based mask defect printability analysis system

A mask defect printability simulation server provides simulations, one-dimensional analysis, and reports to multiple clients over a wide area network, such as the Internet. This network-based simulation server allows a client to leverage a core of highly-trained engineers. Additionally, the network-based simulation server can be easily supported since only a single source for the tools associated with the simulation server is necessary for multiple clients. A client can access the simulation server using a standard personal computer having a browser, thereby eliminating the need for client to maintain an expensive database for the server. Finally, in the network-based simulation server, multiple users can view the same mask defect image and provide real-time comments to each other as simulation and analysis are performed on the defect image, thereby encouraging problem solving and decision-making dialogue among the users.

Method and apparatus for a network-based mask defect printability analysis system

System and method of providing mask quality control

As Optical Proximity Correction (OPC0 and Phase Shifting (PSM) become more and more commonly used for producing smaller features on wafer, the photomask (reticle) manufacturing, that is mask writing, inspection and repairing, and quality assurance become more challenging for both mask shops and wafer fabs. Consequently, a powerful defect analysis tool is needed to determine which defect is a nuisance defect, which defect needs to be repaired, and how good is the repair. It should have the capability for defect printability prediction and analysis of defect impact on device performance. In this paper, we will study and characterize the printability prediction of programmed defects on binary OPC masks by the Virtual Stepper System with its newly developed Automated Defect Severity Scoring (ADSS) function. AMD's defect test reticles HellOPC2 were used. The Virtual Stepper simulation and defect impact analysis results (the automatically calculated Defect Severity Score) will be compared to the SEM images and measurements of wafer prints using 193nm lithography. The results demonstrate that the Virtual Stepper System with its ADSS feature can provide its user with an automate, fast and accurate way of analyzing the impact of a defect. The Virtual Stepper System with ADSS function will be a suitable tool for photomask defect critically assessment in mask shops and wafer fabs.

Linyong Pang

Papers

System and method of providing mask defect printability analysis

User interface for a networked-based mask defect printability analysis system

Method and apparatus for a network-based mask defect printability analysis system

System and method of providing mask quality control

Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring