Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Dynamic array architecture

Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

Gate-length biasing for digital circuit optimization

A technique for quantitatively expressing a manufacturing difficulty level of a photomask and for efficiently manufacturing the photomask is provided. A mask manufacturing difficulty level different for each mask layout, product, and mask layer is relatively recognized with a mask manufacturing load index calculated by a mask manufacturing load prediction system, and when layout correction is possible, the final layout is corrected to a layout with a low difficulty level, and a mask ordering party provides a mask manufacturer with information regarding the mask manufacturing difficulty level in an early stage. The mask manufacturing load index is expressed with a defect guarantee load index and a lithography load index.

Method of manufacturing photomask

Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

Methods and systems for determining a position of inspection data in design data space

A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot spots determination.

Method and system for mask optimization

As Optical Proximity Correction (OPC0 and Phase Shifting (PSM) become more and more commonly used for producing smaller features on wafer, the photomask (reticle) manufacturing, that is mask writing, inspection and repairing, and quality assurance become more challenging for both mask shops and wafer fabs. Consequently, a powerful defect analysis tool is needed to determine which defect is a nuisance defect, which defect needs to be repaired, and how good is the repair. It should have the capability for defect printability prediction and analysis of defect impact on device performance. In this paper, we will study and characterize the printability prediction of programmed defects on binary OPC masks by the Virtual Stepper System with its newly developed Automated Defect Severity Scoring (ADSS) function. AMD's defect test reticles HellOPC2 were used. The Virtual Stepper simulation and defect impact analysis results (the automatically calculated Defect Severity Score) will be compared to the SEM images and measurements of wafer prints using 193nm lithography. The results demonstrate that the Virtual Stepper System with its ADSS feature can provide its user with an automate, fast and accurate way of analyzing the impact of a defect. The Virtual Stepper System with ADSS function will be a suitable tool for photomask defect critically assessment in mask shops and wafer fabs.

Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring

A method and apparatus for modeling and cross correlation of design predicted criticalities include a feedback loop where information from the manufacturing process is provided to cross correlation engine for optimization of semiconductor manufacturing. The information may include parametric information, functional information, and hot spots determination. The sharing of information allows for design intent to be reflected in manufacturing metrology space; thus, allowing for more intelligent metrology and reduces cycle time.

Modeling and cross correlation of design predicted criticalities for optimization of semiconductor manufacturing

A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.

Method and system for inspection optimization

A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing.

Kevin Chan

Papers

Method and system for mask optimization

Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring

Modeling and cross correlation of design predicted criticalities for optimization of semiconductor manufacturing

Method and system for inspection optimization

Method and system for process optimization