A review of ground-based robotic systems for the characterization of nuclear environments

This paper presents the total dose radiation characteristics of high voltage LDMOS on SIMOX substrate using a total dose radiation-hard 0.8 mu m SOI CMOS process. The radiation performance is characterized by transistor threshold voltage shifts, transistor leakage currents. The experimental results show that the breakdown voltage of the LDMOS is 38 V, the threshold voltage shifts of front channels are less than 300 mV and the back channel threshold voltage are greater than 19 V at 1 Mrad(Si).

Total Dose Radiation Characteristics of High Voltage LDMOS on SIMOX Substrate

In future systems with relatively unreliable and unpredictable energy sources such as harvesters, the system power supply may become non-deterministic. For energy effective operations, Vdd is an important parameter in any meaningful system control mechanism. Reliable and accurate on-chip voltage sensors are therefore indispensible for the power and computation management of such systems. Existing voltage sensing methods are not suitable because they usually require a stable and known reference (voltage, current, time, frequency, etc.), which is difficult to obtain in this environment. This paper describes an autonomous reference-free voltage sensor designed using an asynchronous counter powered by the charge on a capacitor and a small controller. Unlike existing methods, the voltage information is directly generated as a digital code. The sensor, fabricated in the 180 nm technology node, was tested successfully through performing measurements over the voltage range from 1.8 V down to 0.8 V.

Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments

This paper presents Analog Fault Tolerant University of Seville Debugging System (AFTU), a tool to evaluate the Single-Event Effect (SEE) sensitivity of analog/mixed signal microelectronic circuits at transistor level. As analog cells can behave in an unpredictable way when critical areas interact with the particle hitting, there is a need for designers to have a software tool that allows an automatic and exhaustive analysis of Single-Event Effects influence. AFTU takes the test-bench SPECTRE design, emulates radiation conditions and automatically evaluates vulnerabilities using user-defined heuristics. To illustrate the utility of the tool, the SEE sensitivity of a 13-bits Successive Approximation Analog-to-Digital Converter (ADC) has been analysed. This circuit was selected not only because it was designed for space applications, but also due to the fact that a manual SEE sensitivity analysis would be too time-consuming. After a user-defined test campaign, it was detected that some voltage transients were propagated to a node where a parasitic diode was activated, affecting the offset cancelation, and therefore the whole resolution of the ADC. A simple modification of the scheme solved the problem, as it was verified with another automatic SEE sensitivity analysis.

Automatic Single Event Effects Sensitivity Analysis of a 13-Bit Successive Approximation ADC

Total ionizing dose response of fluorine implanted silicon-on-insulator buried oxide

A 10-bit 50-MS/s reference-fee low power successive approximation register (SAR) analog-to-digital converter (ADC) is presented. An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC (CDAC) is implemented to cancel the offset of the latch-type sense amplifier (SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier, so that the power consumption can be reduced further. The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology. At a 1.5-V supply and 50-MS/s with 5-MHz input, the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW, resulting in a figure of merit (FOM) of 61.1 fJ/conversion-step.

https://iopscience.iop.org/article/10.1088/1674-4926/33/9/095005/pdf

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 m partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary- scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 10 11 rad(Si)/s and a neutron fluence immunity of 1 10 14 n/cm 2 .

https://iopscience.iop.org/article/10.1088/1674-4926/32/7/075012/pdf

A radiation-hardened SOI-based FPGA

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance–voltage (C–V) analysis.

https://iopscience.iop.org/article/10.1088/1674-4926/31/2/026001/pdf

Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

A fast 128K-bit asynchronous SRAM with access time of 25 ns is presented. It used a radiation hardened 0.8-micron CMOS/SOI process with 3 layers of metal. It features 500 muA stand-by current, 20mA@10MHz operating current, 500K rad(Si) total dose tolerant and 2.45times10 11rad (Si)/s dose rate survivability. The circuit operates with ambient temperature from -25 to +125degC and power supply from 4.5 to 5.5V. A 28-pin dual-in-line flat pack package is used

Radiation Hardened 128K PDSOI CMOS Static RAM

A 14-bit low power self-timed differential successive approximation (SAR) ADC with an on-chip multi-segment bandgap reference (BGR) is described. An on-chip multi-segment BGR, which has a temperature coefficient of 1.3 ppm/°C and a thermal drift of about 100 μV over the temperature range of −40 to 120 °C is implemented to provide a high precision reference voltage for the SAR ADC. The Gray code form is utilized instead of binary form mode control to reduce substrate noise and enhance the linearity of the whole system. Self-timed bit-cycling is adopted to enhance the time efficiency. The 14-bit ADC was fabricated in a TSMC 0.13 μm CMOS process. With the on-chip BGR, the SAR ADC achieves an SNDR of 81.2 dB (13.2 ENOB) and an SFDR of 85.2 dB with a conversion rate of 2 MS/s at room temperature and can keep an ENOB of more than 12 bits at a conversion rate of 2 MS/s over the temperature range from −40 to 120 °C.

http://iopscience.iop.org/article/10.1088/1674-4926/32/8/085003/pdf

Liu Zhongli

Papers

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

A radiation-hardened SOI-based FPGA

Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

Radiation Hardened 128K PDSOI CMOS Static RAM

A 14-bit wide temperature range differential SAR ADC with an on-chip multi-segment BGR