物件導向軟體之架構(Object-Oriented Software Construction)探討

From the Publisher:
Real-Time Systems is both a valuable reference for professionals and an advanced text for Computer Science and Computer Engineering students. 

Real world real-time applications based on research and practice

State-of-the-art algorithms and methods for validation

Methods for end-to-end scheduling and resource management

More than 100 illustrations to enhance understanding

Comprehensive treatment of the technology known as RMA (rate-monotonic analysis) methods

A supplemental Companion Website www.prenhall.com/liu

http://user.it.uu.se/~yi/courses/rts/dvp-rts-08/notes/Course-INFO.pdf

Real-Time Systems

This paper describes the scheduling framework for a new operating system called "Quest". The three main goals of Quest are to ensure safety, predictability and efficiency of software execution. For this paper, we focus on one aspect of predictability, involving the integrated management of tasks and I/O events such as interrupts. Quest's scheduling infrastructure is based around the concept of a virtual CPU (VCPU). Using both Main and I/O VCPUs, we are able to separate the CPU bandwidth consumed by tasks from that used to complete I/O processing. We introduce a priority-inheritance bandwidth-preserving server policy for I/O management, called PIBS. We show how PIBS operates with lower cost and higher throughput than a comparable Sporadic Server for managing I/O transfers that require small bursts of CPU time. Using a hybrid system of Sporadic Servers for Main VCPUs, and PIBS for I/O VCPUs, we show how to maintain temporal isolation between multiple tasks and I/O transfers from different devices. We believe Quest's VCPU scheduling infrastructure is scalable enough to operate on systems supporting large numbers of threads. For a system of 24 Main VCPUs, we observe a CPU scheduling overhead of approximately 0.3% when VCPU budget is managed in 1ms units.

/pdf/virtual-cpu-scheduling-in-the-quest-operating-system-3q08s5wrc9.pdf

Virtual-CPU Scheduling in the Quest Operating System

In most operating systems, the handling of interrupts is typically performed within the address space of the kernel. Moreover, interrupt handlers are invoked asynchronously during the execution of arbitrary processes. Unfortunately, this allows for a process?s time quantum to be consumed by arbitrary interrupt handling. To avoid significant impact to process execution and also to respond quickly enough to interrupts, interrupt servicing is usually split into two parts: a "top" and "bottom" half. The top half executes at interrupt time and is meant to be short enough to complete all necessary actions at the time of the interrupt. In contrast, the bottom half can be deferred to a more suitable point in time to complete servicing of a prior interrupt. Systems such as Linux may defer bottom half handling to a schedulable thread that may be arbitrarily delayed until there are no other processes to execute. A better approach would be to schedule bottom halves in accordance with the priorities of processes that are affected by their execution. Likewise, bottom half processing should be charged to the CPU-time usage of the affected process, or processes, where possible, to ensure fairer and more predictable resource management. This paper describes some of our approaches, both algorithmically and in terms of implementation on a Linux system, to combine interrupt scheduling and accountability. We show significant improvements in predictability of a Linux system by modifying the kernel to more accurately account for interrupt servicing costs and more precisely control when and to what extent interrupts can be serviced.

/pdf/process-aware-interrupt-scheduling-and-accounting-49zmlypyn9.pdf

Process-Aware Interrupt Scheduling and Accounting

Multi- and many-core processors are becoming increasingly popular in embedded systems. Many of these processors now feature hardware virtualization capabilities, as found on the ARM Cortex A15 and x86 architectures with Intel VT-x or AMD-V support. Hardware virtualization provides a way to partition physical resources, including processor cores, memory, and I/O devices, among guest virtual machines (VMs). Each VM is then able to host tasks of a specific criticality level, as part of a mixed-criticality system with different timing and safety requirements. However, traditional virtual machine systems are inappropriate for mixed-criticality computing. They use hypervisors to schedule separate VMs on physical processor cores. The costs of trapping into hypervisors to multiplex and manage machine physical resources on behalf of separate guests are too expensive for many time-critical tasks. Additionally, traditional hypervisors have memory footprints that are often too large for many embedded computing systems. In this article, we discuss the design of the Quest-V separation kernel, which partitions services of different criticality levels across separate VMs, or sandboxes. Each sandbox encapsulates a subset of machine physical resources that it manages without requiring intervention from a hypervisor. In Quest-V, a hypervisor is only needed to bootstrap the system, recover from certain faults, and establish communication channels between sandboxes. This not only reduces the memory footprint of the most privileged protection domain but also removes it from the control path during normal system operation, thereby heightening security.

/pdf/a-virtualized-separation-kernel-for-mixed-criticality-17jlr39j0l.pdf

A Virtualized Separation Kernel for Mixed-Criticality Systems

In this paper we analyze the traditional model of interrupt management and its incapacity to incorporate reliability and the temporal predictability demanded on real-time systems. As a result of this analysis, we propose a model that integrates interrupts and tasks handling. We make a schedulability analysis to evaluate and distinguish the circumstances under which this integrated model improves the traditional model. The design of a flexible and portable kernel interrupt subsystem for this integrated model is presented. In addition, we present the rationale for the implementation of our design over conventional PC interrupt hardware and the analysis of its overhead. Finally, experimental results are conducted to demonstrate the deterministic behavior of our integrated model and to quantify its overhead.

/pdf/predictable-interrupt-management-for-real-time-kernels-over-35jpe08n2d.pdf

Predictable Interrupt Management for Real Time Kernels over conventional PC Hardware

Real-time scheduling algorithms like RMA or EDF and their corresponding schedulability test have proven to be powerful tools for developing predictable real-time systems. However, the traditional interrupt management model presents multiple inconsistencies that break the assumptions of many of the real-time scheduling tests, diminishing its utility. In this article, we analyze these inconsistencies and present a model that resolves them by integrating interrupts and tasks in a single scheduling model. We then use the RMA theory to calculate the cost of the model and analyze the circumstances under which it can provide the most value. This model was implemented in a kernel module. The portability of the design of our module is discussed in terms of its independence from both the hardware and the kernel. We also discuss the implementation issues of the model over conventional PC hardware, along with its cost and novel optimizations for reducing the overhead. Finally, we present our experimental evaluation to show evidence of its temporal determinism and overhead.

/pdf/integrated-task-and-interrupt-management-for-real-time-3ba27hkfu1.pdf

Integrated Task and Interrupt Management for Real-Time Systems

In this paper we analyze the traditional model of interrupt management and its inability to incorporate the reliability and temporal predictability demanded by real-time systems. As a result of this analysis, we propose a model that integrates interrupts and tasks handling. We introduce a novel implementation of this model that uses an adaptation of the optimistic interrupt protection technique [12] for achieving predictability and low overhead. The detailed design of a flexible and portable kernel interrupt subsystem for this integrated optimistic model is presented. We make a schedulability analysis to evaluate the optimistic integrated model and perform experiments to verify its deterministic behavior and its overhead

/pdf/predictable-interrupt-scheduling-with-low-overhead-for-real-5uhahkiycv.pdf

Predictable Interrupt Scheduling with Low Overhead for Real-Time Kernels

http://www.scielo.org.mx/pdf/jart/v11n3/v11n3a11.pdf

Comprehensive Comparison of Schedulability Tests for Uniprocessor Rate-Monotonic Scheduling

In this paper we analyze the traditional model of interrupt management and its incapacity to incorporate reliability and temporal predictability demanded on realtime systems. As a result of this analysis, we propose a model that integrates interrupts and tasks handling. We make a schedulability analysis to evaluate and distinguish the circumstances under which this integrated model improves the traditional model. The design of a flexible and portable kernel interrupt subsystem for this integrated model is presented. In addition, we present the rationale for the implementation of our design over conventional PC hardware and the analysis of its overhead. Finally, experimental results are conducted to show the deterministic behavior of our integrated model.

Luis Eduardo Leyva-del-Foyo

Papers

Predictable Interrupt Management for Real Time Kernels over conventional PC Hardware

Integrated Task and Interrupt Management for Real-Time Systems

Predictable Interrupt Scheduling with Low Overhead for Real-Time Kernels

Comprehensive Comparison of Schedulability Tests for Uniprocessor Rate-Monotonic Scheduling

Real-Time Scheduling of Interrupt Requests over Conventional PC Hardware